VSD - Physical Design Flow

Explore the concept of pre-placed cells in physical design flow, showing how fixed block placements, unit reuse, and black-boxing enable efficient floor planning, routing, and chip area utilization.

Learn how pin placement and logical cell placement blockage shape floor planning in VSD's physical design flow, including netlist connectivity, clock considerations, and handshaking between front and back end design.

Bind the netlist to the physical view using the library's shapes, sizes, and timing data, then place cells on the floor plan to minimize interconnect delay.

Explore clock jitter and uncertainty in physical design, analyzing setup timing under single and multi-clock conditions. Examine PLL variations, clock edges, and delays to ensure reliable timing.

Expand the two clocks to a common rising edge, then determine the shortest setup timing window between launch and capture edges across multiple clock scenarios, identifying worst-case margins.

Perform a data slew check by tracing input transitions through CMOS logic and evaluating leakage, switching, and short-circuit currents to keep output transitions between 20 ps and 400 ps.

Explore maze routing with Lee's algorithm to connect two points on a routing grid by labeling adjacent cells and finding the shortest path with minimal twists while avoiding obstructions.

Explore how Lee's algorithm routes a grid with obstacles by labeling cells and selecting the shortest path from source to target, handling DRC and routing constraints.

Explore SPEF header description and the role of parasitic extraction in physical design flow, including how headers, delimiters, units, and vendor specifics organize parasitic data for timing sign-off and RC calculations.

Demonstrate next-generation education technology for VLSI design flow by using OpenRoad and open-source tools to enable tape-outs, hands-on learning, and project-based careers.