VSD - Physical Design Flow

Explore how to compute utilization factor and aspect ratio in the physical design flow, using standard cells, flip-flops, and netlist area to optimize chip floor planning.

Explore the concept of pre-placed cells in physical design flow, showing how fixed block placements, unit reuse, and black-boxing enable efficient floor planning, routing, and chip area utilization.

Explore why pre-placed cells require surrounding decoupling capacitors to manage local power delivery, stabilize voltage, control noise margins, and prevent cross-talk during switching.

Explore power planning in VLSI design, using decoupling capacitors and multiple power supplies to manage voltage drops and ensure signal integrity on a 16-bit bus.

Learn how pin placement and logical cell placement blockage shape floor planning in VSD's physical design flow, including netlist connectivity, clock considerations, and handshaking between front and back end design.

Bind the netlist to the physical view using the library's shapes, sizes, and timing data, then place cells on the floor plan to minimize interconnect delay.

Optimize placement to minimize interconnect length and capacitance between flip-flops using capacitance estimates. Use buffers to break long wires and preserve signal integrity and timing.

Continue placement optimization and perform a Demming timing analysis with ideal clocks, using buffers and abutments to align flip-flop signals and verify setup and hold constraints.

Perform setup timing analysis with ideal clocks, then real clocks, tracing data from launch flip-flop through combinational logic to capture flip-flop within the clock period, including mux and flop delays.

Explore clock jitter and uncertainty in physical design, analyzing setup timing under single and multi-clock conditions. Examine PLL variations, clock edges, and delays to ensure reliable timing.

Expand the two clocks to a common rising edge, then determine the shortest setup timing window between launch and capture edges across multiple clock scenarios, identifying worst-case margins.

Master the timing analysis for circuits with multiple clocks, derive setup-time constraints, and introduce data slew checks to ensure the critical path delays remain under about 390 picoseconds.

Perform a data slew check by tracing input transitions through CMOS logic and evaluating leakage, switching, and short-circuit currents to keep output transitions between 20 ps and 400 ps.

Learn clock tree routing and buffering with the H-tree algorithm to minimize skew, manage RC delays, and preserve signal integrity across flip-flops using clock buffers.

Explore how clock net shielding mitigates crosstalk in physical design, explaining clock skew, glitches, and shielding techniques to protect critical nets and maintain reliable timing.

Analyze static timing analysis with real clocks, focusing on setup and hold times, clock skew, and data propagation from launch to capture flops.

Concludes hold timing analysis, showing how a clock edge launches data to the launch flop and captures it at the capture flop with slack and uncertainty.

Apply demming analysis to multiple clocks and real clocks, identifying common rising edges, shortest windows, and worst-case timing across clock networks to verify setup timing with flip-flops and capture stages.

Explore maze routing with Lee's algorithm to connect two points on a routing grid by labeling adjacent cells and finding the shortest path with minimal twists while avoiding obstructions.

Explore how Lee's algorithm routes a grid with obstacles by labeling cells and selecting the shortest path from source to target, handling DRC and routing constraints.

Explore design rule check (DRC) essentials for physical design, including minimum wire width and spacing, optical lithography limits, via layout and signaling tricks, with an introduction to parasitic extraction.

Learn how to extract resistance and capacitance and present them in the IEEE 1481-1999 SPEF standard format for parasitic extraction, including net mapping and coordinates.

Explore SPEF representation of a net by detailing driver and receiver connections, net naming, and distributor resistances and capacitances in physical design flow.

Learn how to represent distributed resistance and capacitance in SPEF, including net naming, line numbers, and capacitance and resistance values, for accurate physical design flow.

Explore SPEF header description and the role of parasitic extraction in physical design flow, including how headers, delimiters, units, and vendor specifics organize parasitic data for timing sign-off and RC calculations.

Demonstrate next-generation education technology for VLSI design flow by using OpenRoad and open-source tools to enable tape-outs, hands-on learning, and project-based careers.