VSD - Custom Layout

select a silicon substrate with low doping to form active transistor regions and isolate pockets using silicon dioxide grown by local oxidation of silicon, protected by photoresist masking.

Gain insight into forming n-well and p-well regions through protective masking, boron and phosphorus implantation, and high-temperature diffusion to create active transistor areas.

Learn the fabrication steps to form a gate terminal in VSD custom layout, including controlling gate oxide, doping concentration, and polysilicon gate through deposition, implantation, and etching.

Explore lightly doped drain formation for mos devices, detailing phosphorus and arsenic implantation, masking, and spacers to create B-plus, B-minus regions while mitigating hot carrier and short-channel effects.

Explore source and drain formation through a thin screening oxide and ion implantation. Learn how arsenic, phosphorus, and boron implants and high-temperature diffusion create doped regions and model contacts.

Build contacts by etching the rim and exposing gate, source, and drain to enable local interconnect formation through sputtering of high-resistivity material.

Master higher level metal formation in CMOS by detailing surface topography handling, phosphorus and boron doping effects, chemical mechanical polishing, contact point creation, photoresist removal, and multi-level aluminum interconnects.

Explore how magic represents fabrication data as non-overlapping cells through corner stitching, using magic and tech files to model planes, solids, and space coordinates.

Explore how planes and tiles form the model plane and active plane, showing overlaps, substrate-metal contacts, diffusion, and coordinates that map active areas.

Explore active tile types and tech file content in the VSD custom layout course, including polysilicon, diffusion, rediffusion, diffusion cortex, polysilicon contact, and metal and substrate contexts.

Understand how contacts and styles encode layout connections, including context, diffusion, and substrate contacts, with color coding and numbering that designers use for extraction.

Explore how to extract circuit parameters by mapping connectivity and electrical signal flow between type lists, active plane, model, and diffusion, guiding spice extraction and DRC-informed fabrication.

Explore DRC and lambda design rules, determine minimum feature sizes, and verify polysilicon and metal spacing against foundry constraints using lithography limits and design rule checks.

Learn poly extension and poly to diffusion spacing rules in VSD custom layout, including the active trilemma, lambda requirements, and DRC checks for transistors.

Learn poly to diffusion spacing and diffusion contact width rules, including transistor overlap, touching constraints, lambda-based spacing, and how foundry rules guide alignment and DRC checks.

Explore metal1 width and poly to metal1 spacing rules in the context of layout design, including drc behavior, polysilicon to metal spacing, and rule validation.

Explore contact spacing and minimum active width rules within VSD custom layout, applying DRC checks to ensure proper spacing between active or diffusion contacts, substrate contacts, and lambda-based sizing.

Extract parasitics from the most logical load, generate SPICE netlists, and run SPICE simulations to compare delay and behavior against ideal definitions, guiding layout decisions.

Explore Euler paths and Euler circuits, where every edge is used at least once; circuits start and end at same vertex and use each edge exactly once, under degree requirements.

Learn how to create a stick diagram for CMOS layouts by converting transistors into diffusion sticks (red/green), polysilicon gates (red), and blue power rails (vdd/vss), with diffusion contacts and DRC.

Derive the actual dimensions from the stick diagram by defining polysilicon and active regions, their extensions, and spacing, then validate with drc rules and lambda values.

Develop a pre-layout CMOS design mindset by translating series and parallel transistor networks into complementary logic, and validate with Spice simulations to ensure function, timing, and parasitic effects match layout.

Explore building a stick diagram for a multi-transistor layout, highlighting diffusion and continuous connectivity. Examine how polysilicon, source, drain, and contacts establish transistor connectivity and fabrication-ready patterns.

Explore constructing Euler's path for Fn by input gate ordering in a MOS transistor layout, arranging polysilicon inputs to cover every edge and optimize the circuit.

Explore how to build a simplified stick diagram for a custom layout, using new gate input ordering, diffusion areas, and poly order to connect sources and drains efficiently.

Construct an abstract layout from the stick diagram by defining diffusion and polysilicon regions, lamda spacing, context, and contacts, then set real time dimensions.

Derive actual dimensions for Fn using DRC rules, calculating spacing and active area across polysilicon edges, diffusion, and contacts, with lambda references for layout elements.

Script a custom layout by setting x and y axes and origin, then create lamda-spaced substrate contacts, diffusion and anvil areas, and lead geometry with turtle-based steps.

Master final layout techniques in VSD - custom layout, using scripts to build and label substrate and input/output connections, including power strips, and prepare a SPICE circuit extraction.

Extract the spice netlist and run prelaunch and post-layout simulations to compare delays and parasitics, validating the layout against design goals and results.