VSD - Signal Integrity

Name: VSD - Signal Integrity
Rating: 4.5 (574 reviews)

VLSI - Real and practical steps to build chip with minimum Signal Integrity issues!!

Created byKunal Ghosh

Last updated 1/2017

English

What you'll learn

To Learn Chip Design with minimal Crosstalk in the circuits.
To Design a Chip with minimal errors.

Course content

10 sections • 42 lectures • 6h 34m total length

Introduction8:16

Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction9:16
Impact of Crosstalk Delta Delay on Clock Skew9:42
Setup Timing Analysis Using Real Clocks10:13
Impact of Crosstalk Delta Delay on Setup Timing9:14
Crosstalk Delta Delay - Aggressor Victim Switching in Same Direction8:39
Hold Timing Analysis Using Real Clocks9:19
Impact of Crosstalk Delta Delay on Hold Timing8:27
Examine how crosstalk alters delta delay and hold timing, causing positive or negative slack, and outline strategies to anticipate and mitigate cross-talk effects.

Which Capacitance is dominant for 0.1um and below process
What is the NMH and NML of the below Noise Curve ?
Which of the below scenario is correct ?
Which Scenario impacts the Victim "the least" ?
Mark Potentially Unsafe Glitches among the below !!
Identify Potentially Safe Glitches !!
which of below bucket/s are prone to glitch ?
What is the Setup Slack between 'A' and 'B' ? (Clock Period 'T' = 70ps)
What is Hold Slack between 'B' and 'C' ?

Requirements

Basic of VLSI and Chip Design

Description

Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three.

Crosstalk is the interference caused due to communication between the circuits

Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.

Course Details:
•Reasons for Crosstalk

•Introduction to Noise Margin

•Crosstalk Glitch Example

•Factors Affecting Glitch Height

•AC Noise Margin

•Timing Window Concepts

•Impact of Crosstalk on Setup and Hold Timing

•Techniques to reduce Crosstalk

•Power Supply Noise

Who this course is for:

VLSI Engineers keen to Learn Backend of Chip Design
Physical Design Engineer
Students Learning VLSI Engineering

VSD - Signal Integrity

What you'll learn

Explore related topics

Course content

Introduction1 lecture • 8min

Crosstalk - Why and How Crosstalk occurs in a CHIP ??6 lectures • 56min

Glitch Examples And Factors Affecting Glitch Height7 lectures • 1hr 9min

Tolerable Glitch Heights and Introduction to AC Noise Margin7 lectures • 1hr 5min

Timing Windows5 lectures • 47min

Crosstalk Delta Delay Analysis7 lectures • 1hr 5min

Noise Protection Technique3 lectures • 29min

Power Supply Noise And Power Mesh Solution5 lectures • 47min

Summary1 lecture • 8min

Quiz and Evaluation0

Requirements

Description

Who this course is for: