VSD - Clock Tree Synthesis - Part 1
4.2 (514 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
2,419 students enrolled

VSD - Clock Tree Synthesis - Part 1

VLSI - Building a chip is like building a city!!
Bestseller
4.2 (514 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
2,419 students enrolled
Created by Kunal Ghosh
Last updated 5/2016
English
English [Auto-generated]
Current price: $65.99 Original price: $94.99 Discount: 31% off
5 hours left at this price!
30-Day Money-Back Guarantee
This course includes
  • 4 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • CTS Quality Checks (Skew, Power, Latency, etc.)
  • H-Tree
  • Quality Check of H-Tree
  • Clock Tree Buffering
  • Buffered H-Tree
  • H-Tree with uneven spread of Flops
  • Advanced H-Tree for Million Flops
  • Power Aware CTS (clock gating)
  • Static Timing Analysis with Clock Tree
Requirements
  • Individuals having Basic Knowledge of Electrical and Electronics
Description

Clock Tree Networks are Pillars and Columns of a Chip.

With these series of lectures, we have explored on-site concepts applied in VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits.

The videos will develop an analytical approach to tackle technical challenges while building Clock Tree.

Who this course is for:
  • Individuals keen to learn about VLSI and Chip World
Course content
Expand all 25 lectures 03:57:26
+ Clock Tree Quality Check Parameters
7 lectures 01:07:23
Skew and Pulse Width Check
10:02
Duty Cycle and Latency Check
10:15
Latency and Power Check
10:20
Power Check Continued
09:54
Power and Crosstalk Quality Check
10:46
Delta Delay Quality Check
08:32
Glitch Quality Check
07:34
+ H - Tree
3 lectures 29:30
H-Tree Algorithm and Skew Check
09:41
H-Tree Pulse Width and Duty Cycle Check
09:51
H-Tree Latency and Power Check
09:58
+ Clock Tree Modelling and Observations
4 lectures 39:12
Clock Tree Modelling
09:26
Clock Tree Building
10:21
Clock Tree Buffering
09:58
Clock Tree Observations
09:27
+ Buffered H - Tree
9 lectures 01:29:52
H-Tree Buffering Observations
11:06
H-Tree Skew Check
10:54
H-Tree Pulse Width Check and Issues with Regular Buffers
09:13
CMOS Inverter PMOS/NMOS Switching Resistance Difference
10:26
CMOS Inverter PMOS/NMOS Matching Switching Resistance Solution
09:51
H-Tree with Clock Buffers and Pulse Width Check
10:48
H-Tree Duty Cycle, Latency and Power Checks
09:28
Dynamic Power and Short Circuit Power
09:46
Leakage Power
08:20
+ Conclusion
1 lecture 01:24
Conclusion and next topics!
01:24
+ Interview Questions
0 lectures 00:00

Skew
1 question
Buffer Levels
1 question
Latency
1 question
Clock Gating
1 question
Setup Slack
1 question
Setup Slack - I
1 question
Short Circuit Power
1 question
Delay Table
1 question
Leakage Current
1 question
Total Chip Power
1 question