VSD - Clock Tree Synthesis - Part 2
4.3 (273 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
1,618 students enrolled

VSD - Clock Tree Synthesis - Part 2

VLSI - Building a chip is like building a city!!
Bestseller
4.3 (273 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
1,618 students enrolled
Created by Kunal Ghosh
Last updated 8/2016
English
English [Auto-generated]
Current price: $65.99 Original price: $94.99 Discount: 31% off
5 hours left at this price!
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This course includes
  • 4 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • CTS Quality Checks (Skew, Power, Latency, etc.)
  • H-Tree
  • Quality Check of H-Tree
  • Clock Tree Buffering
  • Buffered H-Tree
  • H-Tree with uneven spread of Flops
  • Advanced H-Tree for Million Flops
  • Power Aware CTS (clock gating)
  • Static Timing Analysis with Clock Tree
Requirements
  • Individuals having Basic Knowledge of Electrical and Electronics
Description

This course is a follow-up course of "VLSI Academy - Clock tree synthesis - Part 1". So its highly recommended to go through Part 1 of clock tree synthesis

Clock is a critical part of any VLSI chip, and this course takes you to the advanced level of building a clock tree from scratch for millions of flop. 

While we plan to add some experimental videos and courses very soon, as a supplement, this one has real time examples and problems that you see on a real chip, and even solutions to those problems

The course is structured in below format:

1) Introduction

2) Clock tree optimization checklist

3) How to build clock tree for uneven spread of clock end-points

4) Power aware clock tree synthesis

5) Static timing analysis with real clocks

Sounds interesting !! Right !! So get in and have the greatest learning experience like you had never before

See you in class!!

Who this course is for:
  • Individuals keen to learn about VLSI and Chip World
Course content
Expand all 25 lectures 04:05:34
+ Clock Tree Optimization Checklist
5 lectures 46:25
Optimization Checklist
09:48
Short Circuit Current Reduction Technique
10:34
Clock Tree Optimized
09:41
Optimized Clock Tree Power And Latency Check
06:47
+ Uneven Spread of Clock Endpoints
4 lectures 42:05
Clock Tree for Uneven Spread of Clock End Points
09:55
Logical to Physical Connections
10:11
Checklist
10:47
Advanced H-Tree for Million Flop clock endpoints with uneven spread
11:12
+ Power Aware Clock Tree Synthesis
9 lectures 01:31:10
Introduction to clock gating cells
09:10
Introduction to Delay Tables
11:12
Delay Table Usage - I
09:21
Delay Table Usage - II
09:30
Clock Gating Technique using AND Gate and Skew Issue
10:29
Solution to Skew Issue
10:03
Clock Gating technique using both AND and OR gate
09:49
Clock Gating Technique using universal NAND gate
10:40
Clock Gating Technique on real Chip and its impact on Power
10:56
+ Static Timing Analysis
5 lectures 52:02
Setup Timing Analysis with Real Clocks
09:48
Introduction to Data Arrival Time, Data Required Time and Slack
11:12
Impact of unbalanced Skew on Setup Time
10:00
Hold Timing Analysis with Real Clocks
09:43
Impact of unbalanced Skew on Hold Time
11:19
+ Summary
1 lecture 12:26
Topics Learned and More to come!!
12:26