VSD - Circuit Design & SPICE Simulations - Part 1

Name: VSD - Circuit Design & SPICE Simulations - Part 1
Rating: 4.4 (709 reviews)

Learn how things got started in VLSI

Created byKunal Ghosh

Last updated 1/2017

English

What you'll learn

Understand, in brief, Physics of MOSFET
Run SPICE simulations on your own and test your own circuits
Get better understanding of Timing Analysis
Learn VLSI from scratch to advanced (this includes my other courses as well)

Course content

7 sections • 30 lectures • 3h 50m total length

Why do we need circuit design and SPICE simulations?10:30
Unpack circuit design and SPICE simulations, using MOS transistors and logic gates to understand how transistor connections yield functionality and how SPICE models produce delay and output characteristics.
Introduction to basic element in circuit design - NMOS9:27
Explore the NMOS transistor as the basic circuit element, including its substrate, diffusion and isolation regions, source and drain, gate oxide, body terminal, and how threshold voltage informs SPICE models.
Strong inversion and threshold voltage9:19
Increase the gate voltage to drive depletion and then strong inversion, forming a continuous source-to-drain channel, while body bias (Vsb) shifts the threshold voltage and depletion behavior.
Threshold voltage with positive substrate potential8:18
Explore how positive substrate bias (VSB) raises the threshold voltage via the body effect, altering depletion, inversion, and gate-to-source needs in MOS devices.

Resistive region of operation with small drain-source voltage9:48
Examine the resistive region of a MOSFET, where gate voltage forms a conducting channel and creates a nonuniform channel voltage that shapes the drain current in SPICE simulations.
Drift current theory8:35
Explore drift current theory in a MOSFET, deriving current from carrier velocity and charge under a gate-induced channel voltage, while considering diffusion current, gate oxide capacitance, and SPICE-focused modeling.
Drain current model for linear region of operation9:41
Derive a simple drain current model for a mosfet's linear region to drive SPICE simulations using mobility, electric field, and channel length.
SPICE conclusion to resistive operation4:27
Explore how gate voltages affect drain current using SPICE simulations, sweeping VGX from 0 to 2.5 to identify the linear region, then examine the saturation region.
Pinch-off region condition9:44
Explore how increasing drain-to-source voltage affects pinch-off, surface inversion, and the channel in a MOSFET. Learn how VGX, VDX, and threshold voltage determine saturation and guide SPICE modeling of current.
Drain current model for saturation region of operation9:28
Explores a drain current model for the saturation region, explains velocity saturation effects, and introduces SPICE simulations to validate a constant-current behavior across varying gate and drain voltages.

Basic SPICE setup9:38
Explore how spice acts as a circuit engine with built-in transistor models, how to feed correct model parameters and netlists, and how technology constants drive accurate delay simulations.
Circuit description in SPICE syntax9:14
Learn to write a Spice netlist and define nodes for MOSFETs, resistors, and voltage sources, with proper values and node naming, then link to a technology file for transistor dimensions.
Define technology parameters9:24
Define technology parameters and plug in spice models to drive the SPICE engine, package model files, and run voltage sweeps to simulate current in the linear and saturation regions.
Standard technology file2:30
First SPICE Simulation10:07
SPICE deck for 1.2u Technology node0:14

SPICE simulation for lower nodes (250nm)9:35
Explore SPICE simulations for 250 nm devices, analyzing DC transfer characteristics across linear, saturation, and cutoff regions, and compare width and length effects on drain current behavior.
SPICE deck for 250nm Technology node0:14
Drain current vs gate voltage for long and short channel device9:49
Explore Spice simulations of drain current versus gate voltage for long- and short-channel devices, revealing a quadratic Id vs Vg relationship at 2.5 V and velocity saturation.
Id-Vgs SPICE deck for 1.2u technology node0:14
Id-Vgs SPICE deck for 250nm technology node0:14
Velocity variation at lower and higher electric fields9:09
Explore how velocity varies with electric field, transitioning from linear to saturation, and how velocity saturation shapes short‑channel device models.
Velocity saturation drain current model9:32

MOSFET as a switch9:31
Introduction to standard MOS voltage current parameters10:09
PMOS NMOS drain current v/s drain voltage10:18
Explore the drain current of pmos and nmos transistors as a function of drain voltage, and analyze CMOS voltage transfer characteristics using SPICE simulations, focusing on gate-to-source voltage and threshold.
Step1 - Convert PMOS gate-source-voltage to Vin9:55
Step2 & Step3 - Convert PMOS and NMOS drain-source-voltage to vout8:48
Convert the PMOS and NMOS drain-source voltage to the output voltage, derive transfer characteristics as a function of input and output voltages, and set up SPICE simulations.
Step4 - Merge PMOS - NMOS load curves and plot VTC10:56
Learn to merge pmos and nmos load curves to plot cmos voltage transfer characteristics and locate the intersection that defines cutoff, linear, and saturation, then use dc spice to validate.

Requirements

Basic understanding on Industiral physical design flow, clock tree synthesis and static timing analysis to get applications of this course
Even if you are not aware of above one's, that's even better, you can start from scratch

Description

So, you are a professional in VLSI, doing tons of tapeouts and accurate timing analysis.

OR, say, you are a student, who already went through my previous courses on clock tree synthesis, physical design flow and crosstalk,

But, sit back, and give it a thought "Have you done it all?" "Did you know, where does the delay of a cell actually comes from?" "We have learnt about delay models, but are the models accurate?" "How do you verify, if what you are doing in static timing analysis, is correct?" and many more.

These are some of curious questions we wonder about, but hardly find any answers. Even if we found the answers, as a passionate learner, we are still more curious to do some practical things on our own.

And, here's the answer to all of them. SPICE (Simulation Program for Integrated Circuit Emphasis). This course has answers to almost all questions that you might have as a serious timing analyst

So let's get started and keep those questions coming in the forum, and I will answer all of them.

See you in class !!

Who this course is for:

Anyone interested to know, what drives this $Billion VLSI industry
Anyone looking to do some practical and hands-on work on SPICE simulations
Any professional already doing Static Timing Analysis and wants to go into details of delay models
Anyone looking to stay for a long time in VLSI domain

VSD - Circuit Design & SPICE Simulations - Part 1

What you'll learn

Explore related topics

Course content

Introduction to circuit design and SPICE simulations4 lectures • 38min

NMOS Resistive region and saturation region of operation6 lectures • 52min

Introduction to SPICE6 lectures • 41min

SPICE simulation for lower nodes and velocity saturation effect7 lectures • 39min

CMOS voltage transfer characteristics6 lectures • 1hr

Conclusion and next steps1 lecture • 2min

Quiz0

Requirements

Description

Who this course is for: