Simple AXI bus Design using Verilog HDL

Name: Simple AXI bus Design using Verilog HDL
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AXI in easy understand

Created bySurender Reddy T

Last updated 12/2023

English

English [Auto],

What you'll learn

Concept of AMBA bus protocol
Concept of AXI Bus
Design and implementation of AXI bus using Verilog HDL
Verification of AXI bus

Course content

4 sections • 17 lectures • 1h 3m total length

Introduction2:37
Explore the amba protocol basics and axi bus design with verilog hdl, covering ax signals, handshake, write and read processes, and verification via a test bench.
AMBA introduction1:38
Learn about Amba, an open on-chip interconnect standard for system-on-chip designs, covering axi, hp, and apb buses and how high-speed and peripheral interfaces connect processors, memory, and peripherals.
Comparision between AHB, AXI, APB2:57
Compare AHB and AXI: AHB is a single-channel bus with one active master at a time, while AXI uses multiple channels with read/write paths and separate address and data lines.

Introduction to AXI1:22
Master the AXI bus architecture with high performance and low latency designs. Understand its flexible interconnect, separate address and data phases, and master-slave transfers with unaligned and out-of-order support.
AXI channel Architecture of Read/writes4:22
Master and slave exchange data across the axa bus through five channels—write address, write data, write response, read address, and read data—using valid and ready handshakes.
AXI signals1:13
Explore AXI signals, including global clock and reset, five channels, and master–slave signal origins; identify read address and read data signals, and the role of the ready and response signals.
Handshaking signals1:46
Signal Diagram5:09
This lecture describes AXI data transfer between modules via AXI master and slave, detailing address, write/read addresses, data, valid and ready handshakes, id, and burst length and size.
Write process Timing diagram2:12
explain the write process timing diagram for AXI bus, showing how the master provides write address and data with valid signals and uses b valid and ready for the response.
Read process Timing diagram2:12
Outlines the AXI read process timing diagram, where the master provides a read address with valid, the slave returns data with read valid, and the master asserts read ready.
Dependencies between channel handshake signals1:42
Map dependencies between channel handshake signals in the simple axi bus design, using single headed and double headed arrows to explain the sequencing of valid and ready events.

AXI state machine for write & read0:33
master the axi state machine for write and read cycles in verilog, detailing four states for write, three states for read, including address, data, response, and idle, plus programming guidance.
AXI Master/Slave Block diagram and Write/read process2:23
Explore the AXI master/slave block diagram and understand how write and read processes transfer data between memory modules through the slave, using start signals and interface signals.

Design of AXI bus using verilog HDL- write process18:11
Design an AXI write process in Verilog by building master and slave write units. Implement memory interactions, address/data handshakes, and state machines for address, data, and response phases.
Design of AXI bus using verilog HDL- Read process11:58
Learn to implement the AXI read path in Verilog with a master and slave read unit, using an idle-address-data state machine and arvalid/arready handshakes, including zeroed memory.
AXI master & slave1:56
Build the AXI master and AXI slave by merging the master write unit and master read unit, save the modules, and prepare a testbench to simulate and run the design.
Test bench & simulation1:35
Write and simulate a testbench for a simple axi bus design using Verilog HDL, initialize clock and reset, and observe master and slave outputs via waveforms.

Requirements

Verilog HDL

Description

AMBA is an open standard for SoC design created by Arm to allow for high-performance, modular, and reusable designs that work right the first time while minimizing both power and silicon.

This course discusses the AMBA, which introduced the Advanced Extensible Interface (AXI) protocol.

Originally conceived for high-frequency systems, the AXI protocol was designed to meet the interface requirements for a wide range of components, while allowing for flexibility in how those components are interconnected. Suitable for high-frequency, low-latency designs, AXI remains backward compatible with the AHB and APB from the previous AMBA revision.

Understanding AXI will give you deep insight into how an SoC works while making you a versatile and well-rounded designer.

Recall that the AHB (Advanced High-Performance Bus) is a single-channel bus that multiple masters and slaves use to exchange information. A priority arbiter determines which master currently gets to use the bus, while a central decoder performs slave selection. Operations are performed in bursts that can take multiple bus cycles to complete. Every burst transfer consists of an address and control phase followed by a data phase.

AXI was designed with a similar philosophy but uses multiple, dedicated channels for reading and writing. AXI is burst-based like its predecessor and uses a similar address and control phase before data exchange. AXI also includes several new features including out-of-order transactions, unaligned data transfers, cache support signals, and a low-power interface.

You can refer to AMBA AXI Protocol v1.0 for a deeper look into the AXI.

Who this course is for:

Intermediate level people who planning to going for job

Simple AXI bus Design using Verilog HDL

What you'll learn

Explore related topics

Course content

Course Introduction3 lectures • 7min

AXI bus8 lectures • 20min

Implementation of Simple AXI bus2 lectures • 3min

Source code4 lectures • 34min

Requirements

Description

Who this course is for: