Embedded Fun with RISC-V, Part 1: The RISC-V ISA

Explore what RISC-V means, compare it with other architectures, learn about the RISC-V foundation, get a book recommendation, and hear about an unfortunate incident.

Explore the contrast between CISC and RISC architectures, highlighting CISC's large, multi-purpose instruction sets and microcoded control versus RISC's simple, fixed-length, load-store design with many registers.

Explore the RISC-V five instruction set architecture introduced in 2010 and its simplicity philosophy. See how RISC-V competes with ARM Cortex CPUs in smartphones, with Patterson and Hennessey's influence.

Explore the RISC-V foundation, an academically rooted, unbiased community that maintains the RISC-V instruction set architecture and supports computational efficiency; learn how to join as an individual or company.

Discover the RISC-V Reader, an open architecture atlas that covers the whole instruction set architecture, with free translations in Spanish, Portuguese, and Chinese.

The lecture recounts Arm facing open source backlash over Risk Five, including the risk the basics site with five points against Risk Five, prompting an apology and takedown.

Explore the basics of computer architecture by identifying the CPU, memory subsystem, and input/output subsystem, and learn how the bus architecture connects these blocks to enable external interaction.

Demonstrates how a naive bus architecture uses eight data lines per device, creating growing complexity, inflexibility, and a costly single-path interconnection bottleneck.

The bus architecture offers flexibility to add or remove devices, with masters driving the bus and slaves listening, while the memory map coordinates address, data, and control buses.

Explore the data bus and how its width matches CPU registers, using 8 or 64 lines, to transport operands, results, and external input/output to and from the microprocessor.

Explore how the address bus width defines the addressable memory space, exemplified by 64k needing 16 lines, and how memory maps assign addresses to RAM, ROM, and I/O.

Explore the control bus architecture, including read/write lines, direction of data, the clock line, and chip select lanes that address each slave, emphasizing synchronization and data flow.

Explore how multiple devices share a single bus using tri-state buffers, exclusive enable controls, and high-impedance states to prevent short circuits while masters listen via input buffers.

Explore the memory subsystem, including program memory (non-volatile like ROM or flash) and general-purpose RAM, and the memory hierarchy with cache memory and mass storage devices.

Examine how the input/output subsystem connects a computer to the outside world through memory-mapped and addressable I/O. Compare polling, interrupt-driven I/O, and DMA as strategies to manage data transfer.

Explore the inner workings of the cpu by examining the ALU, registers, data path, and control logic, then cover instruction coding and execution.

Examine the arithmetic logic unit, or ACLU, and how it performs arithmetic and logic operations—such as addition, subtraction, multiplication, division, and bitwise operations on the individual bits of the operands.

Explore how registers store operands and operation results to aid instruction execution, distinct from memory. Learn how architecture-dependent register counts shape data flow to and from the register bank.

Explore how special registers such as the program counter, instruction register, memory address register, and stack pointer coordinate instruction flow, addressing, subroutines, and interrupts within the RISC-V ISA.

Explore the data path in a bus architecture, showing how registers, memory, and instruction register feed operands and constants to multiplexers that route results to memory or back to registers.

Explore how control logic drives the cpu by generating instruction states, selecting data with multiplexers and tri-state buffers, and coordinating alu operations, memory access, and the pipeline.

Explore how a cpu fetches and executes instructions stored in program memory, using binary encoding that embeds the operation, operands, and destination across bytes and constants.

Explore how instruction execution unfolds through fetch, decode, execute, and write back phase, driven by a control logic state machine that governs these steps.

Explore the instruction set architecture as an abstract model of a computer, detailing CPU registers, addressing modes, memory and IO models, plus options like memory-mapped IO, interrupts, and DMA.

Explore how instructions reference data through various addressing modes, including memory locations, variables, constants, and registers. Understand why not every instruction supports every mode and see examples.

Explore common addressing modes in embedded systems, including immediate constants, register, direct and indirect memory access, pre/post increment, relative branches and jumps, and implicit addressing mode, with practical assembly examples.

Explore how instruction sets vary by operand count, from accumulator and two-address to three-address machines, with historical context from the 1970s and examples like MIPS and eight-bit microcontrollers.

Compare Harvard and von Neumann architectures, detailing separate data and instruction memories with dual buses in Harvard versus a single bidirectional bus in von Neumann, for FPGA CPU design.

Explore the RISC-V architecture under the hood, focusing on the 32-bit rv32i base isa, cpu registers, addressing modes, and load-store, little-endian design with modular extensions like m, a, and c.

Explain the riscv register file of 32 32-bit registers, with x0 always zero, and how the application binary interface assigns designated general-purpose roles and follows a separate program counter.

Explore the addressing modes in risk five: immediate, PC relative, register offset, absolute addressing, and how they support jump and link, branch, load and store, and load upper immediate instructions.

Explore the modular RISC-V instruction sets, from base rv32i to rv64i and rv128i, with M, A, C, F extensions and the embedded base isa, plus 16-bit compressed instructions.

Explore rv32 i base instruction encoding across six formats, including register-register (three-address) operations and immediate types. Examine store, branch, and jump formats with pc-relative and split immediates.

Learn how RISC-V instruction encoding uses a code to select formats, with function three and function seven defining operations, while Rs1, Rs2, and Rd encode the source and destination registers.

Explore how RISC-V encodes immediate values, with 12-bit and 20-bit upper formats, and how store, branch, and jump rearrange bits to form full immediates.

Explore the RISC-V reference card and the base integer instruction set, focusing on core formats (r-type, i-type, s-type, b-type) and the similar s-type and b-type encodings with shared immediates.

Explore register operations in the RISC-V ISA, detailing AH format binary operations—add, subtract, bitwise operations, shifts—and set less than comparisons with signed and unsigned variants.

Explore i-type immediate operations in RISC-V, highlighting 12-bit Emem immediate, source and destination register, and binary operations like xor, shift left, logical shift right, and set less than using immediates.

Explore load and store instructions in the RISC-V ISA, covering i-type immediates, byte, half word, and word data sizes, signed and unsigned extensions, and base offset addressing to memory.

Learn how branch instructions in the RISC-V ISA compare two registers to an immediate and update the PC for conditional, flag-free jumps such as beq, bne, blt, bge, bltu, bgeu.

Explore jump instructions in the RISC-V ISA, including jump and link, noting no unconditional jump, a 21-bit immediate, and how jal and jalr update the program counter and return addresses.

Learn how load immediates shift a 20-bit value by 12 bits into a destination register D, enable upper immediate to PC, and review all 47 base RISC-V ISA instructions.

Explore the rv32m multiply extension, adding four multiplications and four divisions. Mul yields the lower 32 bits; mulh, mulhsu, mulhu yield upper half; div, divu, rem, remu return 32-bit results.

Explore the rv32f/d floating-point extension isa, including fused multiply-add/sub, standard arithmetic, load/store, conversions, and the 32 floating-point registers f0–f31.

Explain the fclass instruction: it reads rs1 and writes a 10-bit one-hot mask to d, classifying the floating-point value into categories, including infinities, zero, normal, subnormal, and not a number.

Explore rv32c compressed extension for 16-bit instructions, enabling smaller program memory in embedded systems. Learn how two-bit up codes distinguish compressed from regular instructions, including jump, move, branch, and no-op.

Explore atomic operations as uninterruptible actions and why they matter for locks in multi-threaded and multiprocessor systems. Investigate how software locks introduce overhead compared with hardware locks.

Explore a race condition in a multi-threaded timer system, where update_time and get_time contend over a shared time structure, risking inconsistent hours, minutes, and seconds.

Explore how a race condition arises in a multithreaded system when timer updates interleave, producing inconsistent time values. Protect the critical section with a mutex lock to guarantee mutual exclusion.

Analyze a pseudo assembly lock that reads a lock variable, acquires it by setting it to one when free, and loops until it becomes free; identify the bigger problem.

Explore how naive lock implementations fail due to race conditions between load and store, and learn about mutex techniques like atomic swap and load linked and store conditional in RISC-V.

Explore the rv32a atomic extension, including load reserved and store conditional pairs and atomic swap, to implement locks and protect critical sections in multithreaded systems.

Examine risk five hardware, popular development boards, and the 32 board used in the remainder of this course, plus reading the user manual and data sheet.

Examine SiFive core IP for risk five processors and their hi5 boards, including the hi5 and hi5 unmatched Arduino clone designs, with revision b and discontinued models.

Explore the RISC-V exchange and its developer boards, review options from RV64 IMAC to red board variants, and wait to test a microcontroller with a RISC-V core.

Explore the gd32vf103 board, a low-cost 32 bit risc five microcontroller with Arduino-format pinout, boot jumpers, USB programmer, and a transparent bare-board approach to embedded control.