RISC processor with own Instruction Set Architecture (ISA)

Explore the seven 32-bit general purpose registers, the program counter, and the stack pointer in this RISC ISA, and how they support addressing and push-pop operations.

Discover the instruction types in a risc processor and their addressing modes, including arithmetic, logical, load and store data transfer, and control flow, plus unconditional jumps and conditional branches.

Explore r-type instructions in a risc processor, illustrating seven addressing combinations, a six-bit instruction format, and how add, or, shift, and compare operations encode with registers like r1 and r2.

Explore immediate type instructions in a RISC ISA, showing how immediate values are embedded in instructions, loaded into R1, and combined with arithmetic operations.

Explore j-types of instructions in a RISC processor with its own ISA, detailing unconditional jumps and the 26-bit instruction format.

Explain B-type branch instructions in a RISC ISA, including conditional branches like if equal, if not equal, and BLT, and how comparisons direct program flow to target addresses.

Explore load and store instruction types in a RISC ISA, including instruction formats, how memory and registers interact, and how addressing and displacement influence operation.

We analyze and summarize our own instruction format, decode instruction sequences, and extract fields to simplify programming with clearly defined type and B-type branch instructions.

Explore the architecture of a RISC processor, detailing code memory, program counter, fetch-decode-execute flow, opcode decoding, registers, and data memory with load and store operations.

Explore how the instruction memory unit stores and loads programs, writes code in a notepad, and uses opcode-based formats and control signals to drive a RISC processor.

Examine how the fetch unit selects a line from memory and passes it to the decoder. Analyze how the counter and control logic manage memory access and data delivery.

Understand how the decoder unit splits instruction data into opcode and register fields, and study the instruction format with specific bit ranges for opcode, source and destination, and immediate data.

Learn how the register file supports read and write operations in a risc processor, including address selection, decoder signals, buffering, and the flow of data between registers and memory.

Examine how the ALU works with the decoder and register file to execute add, sub, and xor operations via opcodes and immediate data, including load and branch handling.

Explain how data memory operates in a Harvard architecture, detailing how write and read operations use control signals to transfer data between memory and the registers.

control unit coordinates fetch, decode, and execute cycles by issuing load signals and guiding the decoder, alu, and data memory.