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Design Verification using System Verilog (SV) + Project Demo
Rating: 4.6 out of 5(84 ratings)
3,361 students

Design Verification using System Verilog (SV) + Project Demo

Verification in ASIC Flow, System Verilog Language constructs, use of SV in verification, Testbench and Tests
Created byVLSI Mentor
Last updated 7/2025
English
English [Auto],

What you'll learn

  • IP Verification concepts
  • Learning System Verilog Language for Verification
  • Developing System Verilog based testbench and testcases to verify a given IP
  • A Case study - how to verify an IP using SV

Explore related topics

Course content

2 sections • 12 lectures • 18h 40m total length

  • ASIC Flow, Verilog Vs System Verilog2:02:43

    Compare Verilog and SystemVerilog in the ASIC flow, from front-end design and RTL to synthesis, timing analysis, and design-for-testability, through verification and back-end implementation.

  • System Verilog Features and Data Types1:59:46

    Explore how systemverilog enhances verilog for verification with modular testbenches, interfaces, generators, drivers, and monitors. Learn data types, classes, assertions, constraint randomization, and transaction-level modeling for verification.

  • SV Tasks, Functions and other advanced data types1:56:43

    Learn systemverilog advanced data types, operators, and constructs, including tasks and functions, port connections, aliasing, and procedural blocks, then apply testbench techniques in simulation.

  • Queues, Arrays1:16:30

    Explore SystemVerilog arrays and queues, from packed and unpacked and dynamic and associative arrays to memory organization and testbench modeling.

  • OOPS Concepts and Classes1:59:33

    Explore SystemVerilog object oriented programming, covering data abstraction, encapsulation, inheritance, and polymorphism, and learn to define classes, objects, properties, methods, constructors, static members, and scope resolution.

  • Lab Assignment2:03

Requirements

  • Digital fundamentals
  • Verilog language
  • Basics of Verification
  • Linux commands

Description

System Verilog course content is designed for beginners to experts ;

The modules can be learnt and practiced in couple of weeks:

The detailed course syllabus is as follows: It is split into 2 parts

Section I:

Session 01 • ASIC flow-Design verification and Verilog  Refresh

Lab 1 - Verilog Testbench development

Session 02 •System Verilog Introduction, Data Types

Lab 2 - Programs with Various data types

Session 03 •Operators-Control Statements-loops

Lab 3- SV Constructs practice

Session 04 •Arrays, Queues

Lab 4 - Arrays, Queues Constructs practice

Session 05 •OOPs-Classes-Objects


Section II:

Session 06 •Randomization and Constraints

Lab 6- Randomization

Session 07 •Inter process Communication

Lab 7- Use of mail box, Semaphores and Queues

Session 08 •Interfaces

Lab 8-Use of interfaces, mod port, clocking block

Session 09 • Testbench development

Lab 09- Use of SV constructs for driver/BFM

Session 10 •Code and Functional Coverage

Lab 10-Simulate an example for coverage


Various example codes are explained in the course. Few of the programs are simulated in the industry standard simulators.

A protocol example is also taken and testbench code is developed and test cases are written for the project.

The assignment given helps to practice the code writing and further using for test bench and testcase development

Who this course is for:

  • Internship for BE/MTech (ECE, EEE) students
  • Engineers who are beginners to System Verilog

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