Design Verification using SV-UVM + Project Demo

Name: Design Verification using SV-UVM + Project Demo
Rating: 4.4 (51 reviews)

UVM Testbench development, Test case development, An example Project, simulation using industry standard simulator

Created byVLSI Mentor

Last updated 8/2026

English

English [Auto],

What you'll learn

Learning Universal Verification Methodology(UVM)
How UVM can be used to build test bench for any digital IP?
Developing Test cases using SV UVM for a digital IP
How to simulate the SV UVM test case

Course content

1 section • 17 lectures • 11h 11m total length

UVM Overview32:01
Explore universal verification methodology (UVM) to boost testbench reuse and portability, introducing TLM, constraint randomization, and a modular framework of agents, sequencers, drivers, monitors, and scoreboards.
UVM Components and Objects51:41
Explore the UVM components and objects that form a layered verification environment for the design under test, including agents with sequencers, drivers, and monitors, plus scoreboards and tests.
UVM TLM1:22:01
Explore transaction level modeling in UVM, including packing and unpacking, tlm ports, tlm fifo, and analysis ports to connect producers and consumers.
UVM Factory45:11
Explore how the UVM factory registers and creates components and objects, and how instance and type overrides enable flexible verification without changing core code.
UVM Configuration53:04
Explore hierarchical UVM configuration using config db and resource db to tailor VIP interfaces, agents, sequencers, monitors, and active or passive settings across top level to tests.
UVM Phases52:43
Master the UVM phases from build and connect to end of elaboration, start of simulation, and runtime phases such as reset, configure, main, and shutdown.
UVM reports37:27
Explore UVM reporting in practice, mastering severity, verbosity, and simulation handling to control log output, filtering, and runtime messaging across complex testbenches.
UVM Report Example6:35
Explore a practical UVM report example that demonstrates how to control message verbosity with UVM full and debug settings across run, elaboration, and build phases.
UVM Sequencer and Driver50:47
Explore UVM sequencer and driver concepts to build test benches for APB and UART interfaces, defining data items and sequence items that flow through an agent.
UVM Monitor and Agent43:19
This lecture explains building an APB Uart test bench package by package, detailing directory structure, interface and package definitions, and how the APB Uart agent and monitor interact.
UVM Scoreboard, Test, Virtual Sequencer and Testbench top56:45
Build and configure a uvm based testbench with a scoreboard and virtual sequencer to coordinate test, environment, and agent configurations, ensuring data integrity via analysis ports.
UVM Topology and printing36:01
Explore how to organize a UVM testbench with modular agents, drivers, monitors, and sequencers, and how to print and inspect the top-level topology for debugging.
UVM Sequences-011:00:41
Learn how UVM sequences drive test scenarios in a component-based testbench, using sequence items and sequencers to generate reusable, randomized stimulus for APB and UART verification.
UVM Sequences 021:01:21
Learn to design and implement UVM sequences for APB and UART, drive transactions through sequencers and virtual sequences, and develop test plans with coverage bins for multi-interface verification.
UVM Lab exercises0:51
UVM Project Assignment - APB memory Verification1:08
Solution for UVM Project Assignment - APB Memory Verification0:03

Requirements

Verification principles, Digital fundamentals, Verilog and System Verilog
Linux commands

Description

This course covers the topics, basics of UVM methodology, components, Objects, UVM Factory, configuration, phases, Reports. Step wise approach to build testbench using driver, sequencer, agent, environment, test and top test bench. Building sequences for verifying the features of an example IP. Outcome of this course, one can develop UVM testbench and testcases right from the scratch. The course is also covering an example test bench creation and explains how to write testcases. How to simulate. This is demonstrated with one simulator.

This course is useful for Students, who are studying BE/BTech/MTech in Electronics and communication and want to learn UVM, do internship. Also those who have completed Engineering , can opt for this course and learn UVM, simulate with free tools available in edaplayground.

This is a complete course with project demonstration and contains the assignments to make the UVM learning easy. The agenda is as follows:

Session 01 - UVM Overview

Session 02 - UVM Components and Objects

Session 03 - TLM

Session 04 - UVM Factory

Session 05 - UVM Configuration

Session 06 - UVM Phases

Session 07-1 - UVM Report

Session 07-2 - UVM Report Example

Session 08 - UVM Sequencer, Driver

Session 09 - UVM Agent, Monitor

Session 10 - UVM Test, Scoreboard

Session 11 - UVM Topology

Session 12-1 - Test sequences part 1

Session 12-2 - Test sequences part 2

Assignments

Once you go through the course, you can apply and get job in semiconductor companies as design verification engineer.

Who this course is for:

BE/BTech/ME/M Tech in Electronics and communication
Those want to learn advanced verification methodology for IP verification in ASIC development
Those who wants to do internship in VLSI- Design Verification
To apply for jobs in ASIC Design Verification in Semiconductor companies