VSD - Functional Verification Using Embedded-UVM - Part 1

Explore the makefile concept and labs, learning how comments use hash signs, automate builds with make as a recipe, and manage targets and dependencies through make all and make clean.

Learn the roles of functional specifications and behavioral descriptions in chip design, and how verification flows, abstraction, interfaces, and agile iterations shape designs and project outcomes.

Explore typical system-on-chip architecture, including processors and general blocks, with automated and manual steps from synthesis to physical design, and rising software involvement across verification.

Explore hardware-software partitioning decisions and their impact on chip size, cost, and performance, while using functional and TLM simulation on virtual platforms for module and top-level verification.

Explore hardware-software partitioning and virtual platform verification, using SystemC models to simulate mixed hardware and software modules for early software development and faster prototyping.

Explore chip design and verification as incremental refinement using virtual platforms and SystemC models, covering functional versus timing considerations, transaction-level modeling, and emulation.

Explore functional verification using embedded-uvm, distinguishing frontend modeling from backend synthesis, and learn how verification ensures the spec is met by the actual chip in a software-driven environment.

Explore how outsourcing application-specific logic to a SoC FPGA lets generic blocks stay in silicon while hardware logic goes into the FPGA, delivered as SRM object file and bit stream.

Explain why verification must span hardware and software, from application logic to device drivers, emphasizing system-level testing with virtual platforms and early bug discovery to avoid costly bugs reaching customers.

Explore the corollary of Moore's Law: transistor counts rise, while clock frequency plateaus after 2005, driving heat issues and pushing multicore designs and verification gaps.

Moore's law stalls cpu speed while bandwidth grows, driving hardware-based verification for high-speed networks from Ethernet frames to IP and upper layers, aided by network processors and OSI seven-layer model.

Explain why SystemVerilog is needed over Verilog for modeling network data structures and fragmentation in hardware verification, and how embedded UVM enables dynamic data handling across IP, frames, and packets.

Examine verification tool performance in multicore architectures and cache coherency. Compare static test benches with dynamic UVM layering and layered sequencer for wider, deeper verification needs.

Emulation speeds verification by offloading to hardware, using FPGA mapping or Palladium with software test benches. Understand multi-threading with virtual cores and parallel lines that maintain throughput amid cache misses.

Explore how multicore raises throughput but not latency, and why Embedded UVM uses a shadow architecture with a single fast, multi-threaded simulation aided by on-chip RAM.

Illustrates how shared memory enables multi-threading and parallel data operations while contrasting with separate processes; explains memory visibility, locking, and module hierarchy partitioning in RTL simulation and open-source verification.

Open source verification is becoming a paradigm-changing trend, with Google and Intel embracing open source verification and FPGA-based accelerators.

Explore how applications request memory and load dynamic and shared libraries from the operating system, then examine FPGA managers enabling partial reconfiguration across servers and cloud.

Open source hardware collaboration addresses a looming verification gap as features proliferate. Promote standard crc algorithms, unify toolchains, and enable cloud-based continuous integration with Travis and GetUp.

Open-source hardware is not free; as adoption scales toward billions, revenue flows from maintenance and paid support for open tools like embedded UVM.

FPGA's programmability bridges the design gap by balancing productivity and performance; while manual gate optimization yields faster, power-efficient chips, synthesis enables scalable, flexible hardware with growing popularity.