FPGA Embedded Design, Part 2 - Basic FPGA Training

Define field programmable gate array as a programmable integrated circuit with millions of gates, and show how it can be programmed to become a device from counters to state machines.

Gain an overview of field programmable gate arrays, their logical cells such as lookup tables and flip flops, and how Verilog or VHDL describes behavior for synthesis to a bitstream.

Compare FPGAs to traditional ASICs, which are application-specific integrated circuits, and see that an FPGA lets an engineer program the hardware to implement all required logic.

FPGA comprises interconnects, logic blocks, and input-output blocks that connect hardware, implement logic, and drive pins.

Examine the interior of a logic block, focusing on logic cells and lookup tables, how inputs A, B, C, and D feed truth tables and a multiplexer selects the output.

Explore how logic cells use lookup tables and multiplexers to realize combinational functions for three- or four-inputs, enable arithmetic with a full adder, and create sequential behavior with a flip-flop.

Explore how FPGA interconnects use programmable analog switches (transmission gates) built from MOSFETs to connect horizontal and vertical lines linking inputs, outputs, carry, and clock signals via junctions.

Explore what’s inside I/O blocks, including amplifiers, attenuators, and level detectors. Understand how low internal voltages enable level shifting and protect outputs with ESD and overload protection.

Explain that a large memory implements interconnections and LUT data, making the memory the programmable core of the FPGA, including I/O directions and high-impedance state, with HDL translated by software.

Compare CPLDs by examining how complex programmable logic devices sit between traditional gate arrays and modern FPGAs, with FPGAs using lookup tables, multiplexers, and flip-flops.

Discover how to program an FPGA by describing hardware with schematics, equations, or VHDL or Verilog, compiling to a bitstream, and loading it into the device using design tools.

Identify the two major FPGA manufacturers, represented by a Virtex 2 FBD and Intel/Altera, and compare development tools ISE and Vivanco with Quartus, noting market dominance.

Explore how an FPGA can implement digital hardware, from combinational and sequential logic to full adders and counters, and run soft processors from Intel and Xilinx.

presents the D.L. Tara 0-dash CV board and its features—10 switches, 10 LEDs, 6–7 segment displays, 4 push buttons, and various connectors—plus pricing notes from Tereszcuk, Alturas, and Digi-Key.

Unbox an FPGA dev board, note the ac/dc adapter, usb cable, and software download sticker; identify switches, programming connectors, the dc input with run/program switch, and micro SD card socket.

Explore the DE0-CV board website, learn about the CD-ROM contents with demo applications, the control panel, and Quartus compatibility, and download the CD-ROM zip for setup.

Explore the DE0-CV board CD content, review data sheets for clock circuitry on the FPGA, and skim the board manual for safe connections. Download the demos, load the default application, and use the system builder for easy designs as the guide walks you through.

Browse the user manual to learn the hardware, including the FPGA and USB blaster. Explore two programming methods—Tag programming and active serial programming—using Quartus.

Learn the FPGA development process through three steps: the steps you need to take, the compiler steps, and how to download your code into your SBA.

Create your project, write your code in VHDL, assign the top model's pins, specify timing constraints, then compile and load the design into the FPGA by hand.

Create a project in the IDE by organizing files and a project file, then select the target FPGA or simulator, language, and IP cores.

Write your code by choosing between an rtl schematic true to your design and a technology schematic mapping to fpga parts, and include all ip cores.

Locate pins and assign them with electrical attributes, such as direction (input, output, bidirectional), Schmitt trigger inputs, and pull resistors, using a project file and a tool to configure pins.

Open the compiled design task to review the IO assignment analysis in the bin planner, explore the BGA FPGA package, and read the legend of user assigned IO.

Specify timing constraints by analyzing propagation delays along red and green paths through xor, and, or gates to ensure carry and sum outputs change reliably.

Explore a propagation delays example that shows how simultaneous input changes can cause non-synchronous, glitchy outputs in xor, or, and gates, revealing race effects in combinational circuits.

Explore how propagation delays affect sequential systems, showing how gates and flip-flops require timing constraints to ensure signals settle before a clock edge, preventing race conditions and limiting clock frequency.

Explore how interconnect routing and limited placement impact propagation delays and timing constraints in large FPGA blocks, underscoring why proper timing constraints matter.

The compiler converts your RTL design into a netlist through synthesis, translate, map, and place-and-route, generating the programming file and implementing the design on the FPGA.

Run timing analysis with Quartus Time quest to verify timing constraints, assess design feasibility at target frequencies, and follow the report's recommendations to relax requirements if needed.

Generate a programming file for the FPGA and test designs in RAM for rapid iteration, then deploy to nonvolatile memory for power-on downloads of the final design.

Install quartus prime lite edition from intel/altera, free for windows or linux, with ModelSim for simulation, and select the 17.0 release and supported devices to save space.

Take a guided tour of Quartus Prime, revealing the project navigator, hierarchy view, compiler tool chain, and IP catalog, and compare gate-level and RTL simulations for FPGA design.

Learn to create a new DE0-CV project in Quartus using a template, download and install the design template from the design store, then import the board support into Quartus.

Explore the top-level Verilog template, detailing symbol definitions, conditional port inclusion, and bidirectional inout pins, with examples like GPO lines, LCD arrays, and button inputs.

Build an FPGA app by wiring switch 0 and 1 to an and gate, then route to lcd outputs; add or and xor gates for switches 8 and 9.

Learn the FPGA design compilation pipeline—from analysis and synthesis to fitter, assembler, and programming file generation—while managing timing constraints and interpreting console warnings.

In JTAG mode, connect the board through the JTA connector and program the FPGA with the programmer, watching LEDs and hex displays reflect OR, AND, and XOR logic.

Set the device to active serial programming, select the POS file, and start programming the nonvolatile memory; power cycle to load the configuration at boot, illustrating nonvolatile FPGA behavior.

Restore the factory application on the board by selecting the default file from the CD-ROM, configuring programs, switching to run, and power cycling to return to its original state.

Use the system builder to quickly jumpstart FPGA projects by selecting elements such as LEDs, buttons, and switches, generate the project, and download the compiled bf file to the board.

Describe the FPGA system that takes two 4-bit inputs A and B, shows their hex sum on seven-segment displays, and uses a 50 MHz clock divider to blink an LCD.

Explore the adder design in a Quartus project, detailing top module, wire arrays for a and B, clock, push buttons, and a hex-to-7-segment display driver that shows the four-digit sum.

Learn to blink the Elodie by dividing a 5 mhz clock to generate signals, then use a push button and a multiplexer to drive lcd anodes for persistence of vision.

Explore instantiated modules in the top model, including a clock divider with a 32‑bit counter, a hex to 7‑segment decoder, and a two‑to‑one multiplexer, with gate‑level implementations.

Program the fpga on the board to run an adder demo. Observe the lcd blink and explore hexadecimal arithmetic using switches and the push button.

Explore the schematic rtl demo for fpga embedded design, showing a top model, clock divider, counter, xor and or gates, and a multiplexer driving an lcd blinking application.

Reflect on FPGA concepts like IO blocks, logic blocks, and interconnections, and summarize the design process—from synthesis to timing constraints—deploying designs to a development board via RAM or nonvolatile memory.

Explore timing constraints, design optimizations, and FPGA vendor offerings, including system-on-chip and soft processors, and look ahead to the next course with Quartus-provided IP to gain hands-on experience.

Celebrate finishing this basic FPGA training course and stay curious. Start building applications by choosing a board and observing timing constraints when you deploy hardware.