FPGA Embedded Design, Part 3 - EDA Tools

Explore electronic design automation, automating hardware design with software suites, and compare integrated development environments to FPGA tools used in FPGA design.

Explore examples of eda tools for hardware simulation and pcb design, including Eagle, a design suite for FPGA, Multisim, Ultiboard, and Jacob, an open-source PCB design tool.

Explore software development tools in FPGA design, including text editors, compiler and linker tool chains, debuggers with simulators, source-to-assembly translation, and runtime views of variables, registers, and memory.

Create a project to guide simulation or FPGA implementation, specifying the target chip or board, language for code entry, and third-party IP or libraries to include.

Write your code for FPGA design, use RTL and technology schematics to validate the synthesis net list, include all modules, and use vendor IP cores, many available for free.

Explore the usual compiler steps for FPGA design: translate, map, place, and route. Synthesis handles both simulation and implementation, turning RTL designs into a netlist and generating a programming file.

Download your design into the FPGA's RAM for loads during development, since RAM is volatile and loses data on power-off; for deployment, use non-volatile memory to load at power on.

Explore EDA Playground by Doulos and learn the required setup, with a quick walkthrough and a code example. Note that the playground supports simulation only, not implementation.

Explore setting up the online EDA Playground for FPGA design, including browser and OS requirements, login options with Google or Facebook, and using non-commercial simulators like Icarus.

Run a simulation by selecting a tool or simulator, configure compile and run options, and explore examples and community resources in the FPGA playground.

Walk through the console output and messages in the FPGA embedded design workflow, highlighting the project summary, ticket console, warnings, and design run reports from synthesis to simulation.

Walkthrough of creating and editing a basis three sdc constraints file to map pin associations from the top design to FPGA pins, enable switches and leds, and set IO standards.

Open the hardware manager, connect the board via USB, and auto connect to program the FPGA with the bit file; observe LCD outputs and explore vato tools.

Explore Verilog IDE pin assignment on DE1-SoC and DE2-115 boards. Map inputs and outputs, 10 switches, 4 buttons, a 50 mhz clock, lcd, and seven-segment displays, with signal assignments.