FPGA Embedded Design, Part 4 - Microprocessor Design

Discover computer architecture by examining the three core parts—the memory subsystem, the input/output subsystem, and the CPU—and how bus architecture connects them to form a complete computer system.

Explore how a bus architecture addresses growth in FPGA embedded design by avoiding excessive data lines, improving flexibility, and enabling scalable interconnections.

Explore a bus architecture that enables flexible device addition, with a master driving the data, address, and control buses and slaves obey, via a memory map.

Explain how the data bus width matches the CPU registers, using eight lines for 8-bit CPU or sixty-four lines for a 64-bit CPU, and carries operands, results, input, and output.

Compute the address bus width needed to cover the memory map; for a 64k space (2^16), use 16 lines, and map RAM, ROM, and I/O with assigned addresses.

Explore how the control bus uses a few lines to synchronize timing and control signals, including read/write direction, the clock, and chip enable lines for addressing each slave.

Explains how a shared bus lets multiple devices drive a line at different times using tri-state buffers with an enable to avoid short circuits and release the bus.

Explore the memory subsystem, contrasting non-volatile program memory with general purpose memory (RAM). Examine how memory hierarchy, cache memories, and mass storage devices support data and instruction storage.

Explore the input/output subsystem, including memory-mapped interfaces, polling versus interrupt-driven I/O, and the role of direct memory access in high-performance and embedded systems.

Explore the internal CPU architecture by examining the arithmetic logic unit, general and special purpose registers, the data path, and the control logic; then review instruction encoding and execution.

The lecture explains the arithmetic logic unit, or aclu, as a multi-function unit that performs arithmetic, logical, and shifting operations and uses inputs to select among up to eight operations.

Registers hold data the CPU uses to perform operations, supplying operands and storing results in a register bank, not memory, with names like r0, r1, and r2.

Demonstrate special registers, including the program counter, instruction register, memory address register, and stack pointer, and explain their roles in subroutines, interrupts, and context switches.

Explore the data path as a bus architecture that routes registers, memory, and constants through multiplexers to form operands and destinations, guided by the instruction register and control signals.

Learn how the CPU instruction encoding stores binary instructions in memory, with opcodes and bytes detailing operation, destination, and operands (registers, constants, memory addresses) across MIPS-like architectures.

Explore how a CPU executes instructions through fetch, decode, execute, and write back stages, driven by a control logic state machine with variations across CPUs.

Explore cpu design criteria by comparing structural and behavioral approaches, examining instruction set architecture, addressing modes, and RISC versus CISC decisions for ASIC or FPGA.

Compare structural and behavioral cpu design approaches, from block diagrams and bottom-up modularity to an instruction set architecture driven state machine. Assess how toolchains affect efficiency, reuse, and code clarity.

Explore the instruction set architecture as an abstract computer model, detailing CPU registers, addressing modes, memory and IO models, and options like memory-mapped IO, interrupts, and DMA.

Explore addressing modes, where operands come from memory, a variable, a constant in the instruction, or registers, and learn why some instructions support only certain modes.

Explore common addressing modes—immediate, register, direct, and indirect memory addressing; incremental variants; relative branches and short/long jumps; and implicit addressing with nop and clia.

Explore how the number of operands per instruction shapes processor design, from stack and accumulator machines to two-address and three-address formats, with x64 and MIPS examples.

Compare CISC and RISC architectures, highlighting CISC's large instruction set, many addressing modes, and microcoded control versus RISC's modest set, fixed-length instructions, many registers, and gate-based control.

Compare Harvard and Von Neumann architectures, emphasizing separate data and instruction memories with distinct buses, one read/write and one read-only, and explain the modified Harvard model in modern devices.

Adopt a quick and dirty approach to cpu design by implementing only the needed instructions, while choosing between sisk and risk, Harvard or von Neumann, and enabling future expansion.

Add two numbers by implementing a simple program that takes two bytes as parameters and returns their sum as a byte, as a proof of concept for the eight-bit C.P.U.

Demonstrate a fib function that computes the zero-based nth Fibonacci number using an iterative loop with A, B, and next, handling base cases 0 or 1.

Program 3 calculates a factorial within an eight-bit unsigned cpu, showing that five factorial fits and uses a return byte; a while loop multiplies by x and returns the result.

The lecture outlines the essential instruction set for a microprocessor, including AV instruction, input/output access, immediate addressing with load, CMPD, branches, decrement, transfer, and multiplication for factorial.

Explore how your personal preferences influence CPU design decisions, and learn to make your own choices to shape your CPU throughout the microprocessor design process.

The lecture argues for a two-address instruction model, weighing accumulator and three-address designs, and discusses choosing between multiple addressing modes versus restricting to two operands per instruction.

The lecture weighs CISC vs. RISC, arguing for a RISC-focused design that uses load and store as the primary memory interaction, with most operations limited to register addressing.

Compare Harvard and von Neumann architectures for an FPGA-based soft CPU, explaining why a separate program memory and data memory simplify rtl design and avoid bus complexity.

Envision a configurable cpu with its own memory inside the fpga, instantiable many times, with internal buses that don't require pins and a program-driven control named Jimmy.

Defines four 8-bit registers, a program counter, a stack pointer, and four one-bit flags to support comparisons, with 256-address program and data memories and a compact one-byte instruction format.

Explore Jimmy's memory model, featuring a separate instruction bus module, data memory, a database, and a 256-byte ram inside the Jimmy module, with the CPU as a hard VRT architecture.

Explain the input output model with four registers—R zero, R one, R two, R three—and eight bit input and output ports, using strobe signals to indicate data transfer.

Design your own instruction set and verify its sufficiency with programming example code. Review addressing modes to identify which instructions you used, then note room for growth for this design.

Explain the instruction set encoding for a microprocessor, detailing 24 instructions, 4- and 6-bit opcodes, one- and two-operand formats, and features like indirect addressing, stack operations, and branches.

Add two numbers A and B, return the sum in register zero, with endless loop driven by START and a conditional branch; load inputs into zero and one, output zero.

Examine program example #2, implementing the Fibonacci sequence in Jimmy's assembly language from input X, with register initializations, a while loop, and output in register one.

Explore assembly code for program example #3 that computes X factorial within eight bits, using input in R0, the out accumulator, and a while loop with post decrement.

Review the six addressing modes in Jimmy's instruction set, including register, indirect by register, implicit, immediate, direct (data memory), and absolute addressing for program memory.

Jimmy’s version instruction set includes add, multiply, and move between registers, plus eight more like load immediate, compare with immediate, decrement, input/output, and branch always or on equal.

Explore room for growth in microprocessor instruction sets, comparing four-bit and six-bit up codes, identifying missing operations such as bitwise and/or/xor, branches, and additional addressing modes.

Write cpu rtl code by examining cpu registers, the state machine design, and extracting op codes from instructions to drive the fetch cycle.

Explain a project that blends rtl and behavioral code, detailing a simple jime module with clock, reset, input and output port arrays, and a read-only instruction memory.

Explore the cpu registers and register bank R, including the program counter, stack pointer, and flags: zero, carry, negative, and overflow, plus mem as an array of 256 bytes.

Describe a four-bit, one-hot encoded state machine driving fetch, code, execute, and write back, with an active-low reset and a clocked always block for FPGA design.

Present Jimmy's microprocessor control using fetch, execute, and write back states. Initialize a three-bit state variable named state and drive transitions with a case statement.

Explore how the FPGA embedded design encodes instructions with four-bit and six-bit op codes, covering the register addressing mode, load immediate variants, direct addressing mode, and an implemented nop.

Learn how to extract up codes from encoded instructions using assign statements in hardware description language, distinguishing category one and category two opcodes and their bit positions.

Analyze the fetch cycle in a state-machine cpu, including synchronous reset, initialization of counters and strobes, and category-based instruction decoding to drive the program counter.

Implement the instruction set for the state machine, covering addition, multiplication, load, load immediate, register transfer, move, input/output, compare, and branches, including unconditional and branch-on-equal and signed/unsigned greater-than.

Demonstrate implementing the fetch and execute stages by case-selecting instructions via the instruction register, detailing add, multiply, transfer, compare immediate, and input/output, plus program counter updates.

Demonstrate the addition instruction using AB register addressing, update the destination register with the sum, and compute flag values (carry, zero, negative, overflow) from msb bits, referencing classic CPU manuals.

The multiply instruction uses two 8-bit operands to produce a 16-bit result. The high byte goes to Rb, the low byte to Ra, sacrificing both registers and leaving flags unchanged.

Copy contents from the source register to the target register, a register transfer that updates zero, negative, and overflow flags in eight-bit processor, and can exit to fetch next instruction.

The lecture explains that the NOP does nothing and moves to the next address in the fetch state, suggesting optimization by checking the instruction database for category one opcode.

Load immediate transfers a constant from program memory into the a register, then moves to fetch state, updating zero and negative flags with no overflow.

Explore the decrement instruction in microprocessor design, subtract one, store the result in the target register, and update the flags.

Explain how to route fpga input ports using an input port array and per-port wires, with a strobe signaling a consumed byte to external hardware, inside the Jimmy module.

Explore how an output instruction drives an output port from a register via a strobe, sending a pulse to external hardware and preparing for the next instruction in fetch state.

Examine unconditional branching in FPGA embedded design, focusing on the always branch that updates the program counter to the absolute addressing mode target in program memory.

Explain the branch if higher instruction, comparing unsigned numbers, with the carry and zero flags determining a jump; if true, update the program counter, otherwise proceed.

Explore branch on equal in microprocessor design by comparing two values, setting the zero flag when subtraction is zero, and updating the program counter to jump or proceed.

Finish the system design by integrating the C.P.U, program memory, and three modules, then write each with its own program in machine language, without an assembler or compiler.

Shows a Harvard architecture CPU named Jimmy with a dedicated read-only program memory, an address bus driven by the program counter, performing fetches and using reset and clock signals.

Translate a C function into Jimmy assembly, navigate the machine's instruction set and addressing modes, and adapt logic to input/output constraints for endless embedded loops.

Write the example program #1 in memory using a coding spreadsheet, implementing each instruction with single- and two-byte opcodes for inputs and registers, and using symbols to avoid bit errors.

Examine how the second program encodes two-byte instructions, uses arrows to reference preceding instructions, and analyzes labels, constants, and immediate values in the encoding scheme.

Write the factorial program example #3 using memory-encoded instructions, showing up code symbols concatenated with operand codes and decimal encoding, and highlighting mistakes that mix multiplication and move.

Learn the role of synthesis in FPGA design, then run simulations with a test bench to validate hardware and the microprocessor, avoiding big bank testing and common coding mistakes.

Demonstrates simulated hardware for program #1, wiring registers a and b to inputs and routing the sum to register s via output, driven by strobe signals in the test bench.

Describe simulated hardware for fibonacci and factorial programs using shared hardware. Feed a into input port zero, trigger strobe to s after each calculation, and increment a for next result.

Explore a test bench driven Vivado simulation that exercises a microprocessor design with clock and reset, program memory modules, and strobe-controlled outputs across three example programs.

Demonstrates Vivado simulation of a Fibonacci generator in program #2, wiring input a to fib output, updating the s register, and stepping through the sequence with clock, reset, and strobe.

Vivado simulation for program three uses the top module and test bench with program memory three, compares to program two, and analyzes eight-bit factorial results and the lower-byte overflow.

Explore Quartus simulations for program #1 on Intel or Altera FPGAs. Set test benches as top level, select signals A, B, and S, and run ModelSim.

Watch a Quartus simulation for program two in Qualitest Prime, set the top level entity, select signals, adjust timing to 100 and 1000 nanoseconds, verify Fibonacci sequence up to 233.

Run a Quartus simulation for program 3, adjust radix, and observe 10! wrap to zero, with the lower byte showing factorial values like 1, 2, 6, 24, 120, and 128.