Digital System Design using Verilog HDL

Lecture Description

In this lecture, we will implement a NOT gate using Gate-Level Modelling in Verilog HDL. This is one of the fundamental digital design exercises, helping you understand how primitive logic gates are represented and simulated in hardware description languages.

✅ What you’ll learn in this lecture:

• Basics of gate-level modelling in Verilog.

• Syntax and structure for instantiating a NOT gate.

• Writing the Verilog code for a NOT gate using built-in primitives.

• Creating a testbench to verify the functionality of the NOT gate.

• Observing simulation waveforms for input–output verification.

This lecture is designed for beginners in Verilog and those who are starting their journey in Digital Design / VLSI, giving you a solid foundation to progress towards more complex circuits.

Lecture Description

In this lecture, we will design a NOT gate using Dataflow Modelling in Verilog HDL. Dataflow modelling is an important abstraction in Verilog that allows us to describe circuit behavior using continuous assignments and Boolean expressions, making it more flexible than gate-level modelling.

✅ What you’ll learn in this lecture:

• Introduction to dataflow modelling style in Verilog.

• Using the assign statement to implement logic functions.

• Writing Verilog code for a NOT gate with dataflow description.

• Creating a testbench to verify functionality.

• Simulating and analyzing waveforms to confirm correct operation.

This lecture is ideal for learners who want to move beyond gate-level modelling and gain confidence in writing behavioral expressions for digital circuits in Verilog.

Lecture Description

In this lecture, we will implement a NOT gate using Behavioral Modelling in Verilog HDL. Behavioral modelling is the highest level of abstraction in Verilog, where circuits are described using procedural blocks like always and high-level constructs, making it easier to model functionality.

✅ What you’ll learn in this lecture:

• Introduction to behavioral modelling in Verilog.

• Writing a procedural block (always) to describe the NOT gate.

• Using reg and procedural assignments effectively.

• Creating a testbench to apply stimulus and observe responses.

• Simulating waveforms to validate the NOT gate behavior.

This lecture is especially useful for learners who want to understand how high-level descriptions can be synthesized into hardware, bridging the gap between coding and real-world circuit implementation.

Lecture Description

In this lecture, we will design an OR gate using Gate-Level Modelling in Verilog HDL. Gate-level modelling is the most fundamental way of describing digital logic in Verilog, where we directly instantiate predefined logic primitives.

✅ What you’ll learn in this lecture:

• Basics of gate-level modelling in Verilog.

• Syntax for instantiating an OR gate primitive.

• Writing the Verilog code for a 2-input OR gate.

• Developing a testbench to verify OR gate functionality.

• Running simulations and analyzing waveforms for input–output behavior.

This lecture builds a strong foundation in basic digital logic design, preparing you to model more complex circuits using Verilog HDL.

Lecture Description

In this lecture, we will design a 2-input OR gate using Dataflow Modelling in Verilog HDL. Dataflow modelling allows us to describe logic functions using Boolean expressions and continuous assignments, making it more concise compared to gate-level modelling.

✅ What you’ll learn in this lecture:

• Introduction to the dataflow modelling style in Verilog.

• Using the assign statement to implement an OR gate.

• Writing clean and efficient Verilog code for a 2-input OR gate.

• Creating a testbench to apply different input combinations.

• Running simulations and analyzing waveforms to validate the design.

This lecture helps learners understand how to use Boolean operators in Verilog to model digital circuits at the dataflow level, which is widely used in RTL design.

Lecture Description

In this lecture, we will implement a 2-input OR gate using Behavioral Modelling in Verilog HDL. Behavioral modelling is the most abstract style in Verilog, where circuit functionality is described using procedural constructs such as always blocks and procedural assignments.

✅ What you’ll learn in this lecture:

• Basics of behavioral modelling in Verilog.

• Writing an always block to describe OR gate functionality.

• Using reg variables and procedural assignments.

• Developing a testbench to verify different input combinations.

• Simulating and analyzing waveforms to confirm OR gate operation.

This lecture enables learners to understand how high-level procedural code can represent digital circuits, a skill that is essential for RTL design and synthesis.

Lecture Description

In this lecture, we will design a NAND gate using Gate-Level Modelling in Verilog HDL. The NAND gate is a universal logic gate, meaning that any digital circuit can be built using only NAND gates. Gate-level modelling uses predefined logic primitives to represent hardware directly.

✅ What you’ll learn in this lecture:

• Fundamentals of gate-level modelling in Verilog.

• Syntax for instantiating a NAND gate primitive.

• Writing Verilog code for a 2-input NAND gate.

• Creating a testbench to apply stimulus and verify outputs.

• Simulating and analyzing waveforms to validate NAND gate functionality.

This lecture strengthens your understanding of basic logic design and demonstrates how NAND gates serve as the foundation for building more complex circuits.

Lecture Description

In this lecture, we will design a NAND gate using Dataflow Modelling in Verilog HDL. Dataflow modelling allows us to describe digital circuits using Boolean expressions and continuous assignments, making it more compact and flexible than gate-level modelling.

✅ What you’ll learn in this lecture:

• Basics of the dataflow modelling style in Verilog.

• Implementing a 2-input NAND gate using the assign statement.

• Writing efficient Verilog code with Boolean operators.

• Building a testbench to verify NAND gate functionality.

• Running simulations and analyzing waveforms for input–output verification.

This lecture helps learners understand how to implement universal gates like NAND using Boolean logic expressions, which is essential for RTL design and synthesis.

Lecture Description

In this lecture, we will implement a NAND gate using Behavioral Modelling in Verilog HDL. Behavioral modelling provides the most abstract way of describing a circuit, where functionality is expressed using procedural blocks instead of direct gate instantiations or Boolean equations.

✅ What you’ll learn in this lecture:

• Introduction to behavioral modelling style in Verilog.

• Writing an always block to describe a 2-input NAND gate.

• Using reg variables and procedural assignments for outputs.

• Developing a testbench to verify NAND gate functionality.

• Simulating waveforms to confirm the correct operation.

This lecture is especially useful for learners who want to see how high-level procedural descriptions can represent fundamental digital circuits, preparing them for complex RTL design.

Lecture Description

In this lecture, we will implement a Half Adder using Gate Level Modelling in Verilog HDL. Gate level modelling describes a circuit by directly instantiating logic gates, making it the most structural and hardware-oriented style of coding.

✅ What you’ll learn in this lecture:

• Introduction to gate level modelling style in Verilog.

• Constructing a Half Adder using XOR and AND gates.

• Writing Verilog code with built-in primitive gate instantiations.

• Developing a testbench to validate Half Adder operation.

• Simulating outputs and analyzing waveforms for correctness.

This lecture is ideal for learners who want to understand how basic combinational circuits can be directly mapped using logic gates in Verilog, building a strong foundation for digital design.

Lecture Description

In this lecture, we will implement a Half Adder using Dataflow Modelling in Verilog HDL. Dataflow modelling is a powerful style that uses continuous assignments and Boolean expressions to describe digital circuits, making it more abstract than gate level modelling but still close to the actual hardware behavior.

✅ What you’ll learn in this lecture:

• Introduction to dataflow modelling style in Verilog.

• Describing the Half Adder using assign statements and logical operators.

• Writing Verilog code for the Sum and Carry outputs using Boolean expressions.

• Developing a testbench to verify the Half Adder functionality.

• Simulating and observing waveforms to ensure correct operation.

This lecture is especially useful for learners who want to move beyond gate instantiation and start describing digital circuits in a functional and equation-based style, preparing them for RTL-level design.

Lecture Description

In this lecture, we will implement a Half Adder using Behavioral Modelling in Verilog HDL. Behavioral modelling allows us to describe a circuit’s operation using procedural blocks such as always and if-else statements, making it the most abstract style of modelling.

✅ What you’ll learn in this lecture:

• Introduction to behavioral modelling style in Verilog.

• Using the always block to describe the Half Adder functionality.

• Declaring reg variables and using procedural assignments for outputs.

• Writing Verilog code for the Sum and Carry operations inside procedural logic.

• Developing a testbench to test the Half Adder.

• Running simulations and analyzing waveforms to confirm correct functionality.

This lecture is particularly helpful for learners who want to see how high-level procedural descriptions can implement even the most fundamental digital circuits, providing a solid foundation for complex RTL design.

Lecture Description

In this lecture, we will design and implement a 4-Bit Ripple Carry Adder (RCA) using Verilog HDL. The Ripple Carry Adder is one of the most fundamental multi-bit adders, where multiple Full Adders are cascaded, and the carry “ripples” from the least significant bit (LSB) to the most significant bit (MSB).

✅ What you’ll learn in this lecture:

• Concept of a Ripple Carry Adder and how multiple Full Adders are connected in sequence.

• Writing Verilog code for the 1-bit Full Adder module.

• Building a 4-bit Ripple Carry Adder by instantiating four Full Adders.

• Creating a testbench to apply different input vectors and verify correctness.

• Simulating and analyzing waveforms to observe sum and carry propagation.

This lecture is highly beneficial for learners who want to understand how multi-bit arithmetic circuits are constructed from simpler building blocks, forming the basis for arithmetic logic units (ALUs) in digital systems.

Lecture Description

In this lecture, we will design and implement a Mealy Finite State Machine (FSM) in Verilog HDL to detect the binary sequence 1001. A Mealy FSM generates outputs based on both the current state and the current input, making it efficient for sequence detection problems.

✅ What you’ll learn in this lecture:

• Introduction to Mealy FSMs and how they differ from Moore FSMs.

• Step-by-step state diagram construction for detecting the sequence 1001.

• Writing Verilog code for the FSM using state encoding and always blocks.

• Developing a testbench to verify the detection of overlapping and non-overlapping sequences.

• Simulating outputs and analyzing waveforms to confirm correct sequence detection.

This lecture is especially useful for learners who want to understand how Finite State Machines are applied to real-world problems such as pattern recognition, protocol design, and digital controllers.

Lecture Description

In this lecture, we will implement a Full Adder (FA) using Xilinx ISE 14.7 – one of the most widely used FPGA design tools. A Full Adder is a fundamental combinational circuit that adds three inputs (A, B, Cin) and produces a Sum and a Carry output. Through this lecture, you will learn how to design, simulate, and verify the Full Adder using the Xilinx toolchain.

✅ What you’ll learn in this lecture:

• Introduction to Xilinx ISE 14.7 environment and project setup.

• Writing Verilog code for a 1-bit Full Adder.

• Creating a testbench to apply different input combinations.

• Running behavioral simulation in Xilinx ISE to verify correctness.

• Observing waveform outputs in the simulator.

• Preparing the design for synthesis and FPGA implementation.

This lecture is perfect for learners who want hands-on experience with FPGA design flow using Xilinx ISE, starting from Verilog coding to simulation and synthesis. It builds a strong foundation for implementing more complex digital circuits on FPGA hardware.

Lecture Description

In this lecture, we will learn how to print and observe outputs in Xilinx ISE 14.7 after writing Verilog code and creating a testbench. Instead of using a physical FPGA board, beginners often rely on the behavioral simulator inside Xilinx ISE to check whether their design works correctly.

✅ What you’ll learn in this lecture:

• Setting up a simulation project in Xilinx ISE.

• Writing Verilog code and creating a testbench with $monitor, $display, and $dumpfile statements to print outputs.

• Running behavioral simulation and observing printed outputs in the console window.

• Viewing waveforms using the ISim simulator to visualize signal changes over time.

• Understanding how to interpret simulation logs and timing diagrams.

This lecture is especially useful for learners who want to verify and debug their Verilog designs in Xilinx ISE, by printing outputs to the console and analyzing signals through simulation waveforms.

Lecture Description

In this lecture, we will design and implement a 2-to-4 Decoder using Behavioral Modelling in Verilog HDL. A decoder is a fundamental combinational circuit that converts binary-encoded inputs into a one-hot output, widely used in memory addressing, instruction decoding, and control logic.

✅ What you’ll learn in this lecture:

• Introduction to Behavioral Modelling in Verilog.

• Understanding the working principle of a 2x4 Decoder.

• Writing Verilog code using always blocks and case statements / if-else constructs.

• Using reg variables and procedural assignments to control outputs.

• Developing a testbench to apply all input combinations and verify correct one-hot outputs.

• Simulating and analyzing waveforms for validation.

This lecture is ideal for learners who want to understand how high-level procedural coding can be used to describe and implement combinational circuits like decoders, which are essential building blocks in digital systems.