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IT & Software Hardware Verilog HDL Programming

Digital Design using Verilog HDL programming with practical

design & verification with examples & applications
Rating: 3.8 out of 53.8 (10 ratings)
87 students
Created by Surender Reddy
Last updated 9/2020
English
English [Auto]
30-Day Money-Back Guarantee

What you'll learn

  • Learning Verilog HDL Programming concepts with examples
  • Writing complete design & test bench programming for modules like Memory controllers, FIFO controller, Random data generators, Error detection correction using Hamming code and file representation input & output etc.
  • How to use task & system tasks in Test bench
  • How to draw Finite state machine (FSM) and how to write verilog program for any FSM and Sequence detector FSM

Requirements

  • basic in C-programming
  • basics Digital design ( we are designing digital circuits, but no need of digital knowledge to design a complex circuits)

Description

This is a complete Verilog HDL programming course for beginners as well as higher level, as it is from scratch to the application level. This course not only discuss the concepts in Verilog HDL programming but also discuss the applications.

This course gives clear picture on simulation and writing a test bench using task and system task and illustrated with examples. For that, it provides file based examples like writing data in to file, reading data from file and loading data in to memory. Also some general examples like counter, clock diver using counter, pulse generator and random generator.

This course used to build Finite State Machines (FSM) diagram from the requirements and realization of FSM in to hardware model, then translation of hardware model FSM into verilog code for both Mealy & Moore and demonstrated with examples.

This course also shows some projects like Memory controller, FIFO controller and Error detection & correction using Hamming code. and finally it gives basic knowledge on FPGA's.

Who this course is for:

  • Undergraduate Electronics and computer science engineering students
  • Graduate students who planning their career in VLSI domain front end (Design & verification)
  • Advanced under graduate students, who willing to do project in front end VLSI design

Course content

18 sections • 34 lectures • 3h 58m total length

  • Preview13:35
  • Preview12:49

  • Verilog fundamentals
    10:41

  • VLSI design flow ( FPGA & ASIC)
    03:02

  • Three levels of verilog design Description
    04:45

  • Verilog Language constructs & Data types
    05:42
  • Compiler Directives
    02:29

  • Verilog Program structure
    05:01

  • Gate level modeling
    03:17

  • Data flow modeling
    06:35

  • Behavioral Modeling constructs & procedural blocks
    03:41
  • Assignment statements blocking & non-blocking
    09:07
  • if-else and case construct
    03:58
  • loops
    01:35
  • parallel blocks (fork-join)
    00:42
  • Two Examples - 1. counter 2. clock divider using counter
    03:19
  • D-FF & D-Latch
    02:51
  • Decoder and Encoders
    04:13
  • memory design
    04:06

  • Switch level modeling
    03:59

Instructor

Surender Reddy
Design Verification Engineer
Surender Reddy
  • 3.8 Instructor Rating
  • 10 Reviews
  • 87 Students
  • 1 Course

Having more than 7 years experience in VLSI design having experience in verilog and system verilog & UVM. I worked on protocols like AHB, APB and AXI which are essential modules in VLSI design. I worked on different project covered more than 50 verilog modules. I have experience on FPGA boards, and xilinx Zynq FPGA boards (which having ARM processor in it). I am planning to do future courses on AMBA protocols and General Microprocessor design with our own Instruction Set Architecture (ISA).

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