Complete Verilog HDL programming with Examples and Projects

Name: Complete Verilog HDL programming with Examples and Projects
Rating: 4.1 (376 reviews)

Fundamentals, Design flow, modeling levels, Datatypes, test bench, Tasks & system tasks, FSM, FPGA & examples & Projects

Created bySurender Reddy T

Last updated 6/2023

English

What you'll learn

Learning Verilog HDL Programming fundamental concepts and properties compare to C Language, feature & advantages of Verilog HDL over VHDL
VLSI Design flow ( FPGA & ASIC) and Difference between FPGA vs ASIC
Different design methodologies in Verilog HDL programming with examples
Behavioral modeling with blocking & Non-Blocking concepts and real time examples
Test bench Verilog program with examples
Task & system tasks with examples for random data generator, file based operations and memory load operations, and file representation input & output etc.
Finite state machine (FSM) with example for both Mealy & Moore and Sequence detector FSM
Complete design & test bench programming for Memory controllers
Complete design & test bench programming for FIFO controller
Complete design & test bench programming for Encoder & decoder for Hamming code Error detection correction
Basics of FPGA

Course content

18 sections • 105 lectures • 8h 8m total length

Preview - course content22:30
Sample program on edaplayground13:42

Data flow Modeling : assign statement2:23
Operators1:56
Arithmetic Operators1:21
Logical Operators1:44
Example : Full Adder: Logical operators0:57
Example : Full Adder: Arithmetic operators0:48
Example: Binary to Gray code converter0:52
Logical and , Logical or (&&, ||)1:10
Shift operators : Left/right Shift2:11
Shifting without shift operator , just with concatenation operator1:11
Ternary operator : Example : 2x1 MUX, 4x1 MUX3:01
Relational operators Example: Comparator0:58
Equality (==) , case Equality (===) operators1:58
Reduction operator : Example: Parity Generator1:09

Behavioral Modeling - Introduction6:32
Behavioral Modeling Constructs1:40
Procedural Blocks- initial & always6:38
Example: Clock Generation2:10
Assignment Statements - Blocking & Non-blocking6:19
Mechanism in Non-blocking1:07
Concurrency1:01
Advantage of Non-blocking assignment: Example: swapping1:15
Advantage of Non-blocking assignment: Example : Pipelining4:35
if-else: statement: Example : 4x1 Mux4:09
Case – statement : Example : 4x1 Mux3:40
Advantage of Case over if-else1:04
Loops: while, for, repeat, forever1:15
Parallel blocks - fork-join1:40
Combinational Logic circuits: List of Examples0:44
Example: 8x1 mux with 4x1 and 2x15:27
Example: AND gate using 2x1 Mux1:50
Example: 1x8 Demux0:34
Example: Full Adder & 4-bit Full Adder2:22
Example : 3x8 Decoder and 3x8 Decoder using 2x4 decoder1:42
Example : 8x3 encoder0:25
Example : Priority encoder1:14
Example : Seven Segment Display1:39
Example : ALU0:41
Sequential Logic Circuits: List of Examples1:03
Example: D Flip Flop vs D-Latch1:49
Example: Synchronous Reset D-Flip flop , Asynchronous Reset D-Flip flop1:02
Example : T-Flip Flop1:39
Example : Master-slave JK Flip Flop1:02
Example: Counter2:53
Example: UP/Down Counter3:37
Example: clock divider using counter- Divide by 2,4,8,....1:16
Example: Pulse Generator: Mod-3 pulse generator1:52
Example: Divide by 3 clock2:26
Example : Ring Counter vs Jonson Counter1:45
Example : Shift Registers : SISO, SIPO, PISO,PIPO1:42
Example: LFSR (Linear Feedback Shift Register)- Random Generator4:03
memory design4:06
Block diagram for memory design & verilog program for write - read processes

Requirements

Intension to learn
basic in C Language
basics in Digital design ( not compulsory)

Description

Complete Verilog HDL programming course with a perfect, well structured and concise course for freshers and experienced, as it is from fundamental level to the application level. This course discuss the concepts in Verilog HDL programming and properties compared with C-Language and discussing the features and advantages.

In this course we give information related to VLSI design flow for FPGA & ASIC and gives overview about both.

This course gives information on different styles of programming like Gate level, Data flow, Behavioral and switch level with examples.

This course gives clear picture on verification, i.e. simulation and writing a test bench and some general examples like counter, clock diver using counter, pulse generator.

This courses explains how to write verification models using test benches with task and system tasks with Examples. These examples includes, file based system tasks such as writing data in to file, reading data from file and loading data in to memory and random data generator.

This courses shows clear picture on Finite State Machines (FSM)

how to draw,

how to realize it in to hardware model

how ro translate in to verilog code for both Mealy & Moore FSM with examples.

This course also shows some projects like Memory controller, FIFO controller and Error detection & correction using Hamming code, this improves ability to analyse and approach to Projects.

Finally it gives basic knowledge on FPGA's like core concept how bit file is loaded in to FPGA.

Who this course is for:

Undergraduate Electronics and computer science engineering students
Graduate students who planning their career in VLSI domain front end (Design & verification)
Advanced under graduate students, who willing to do project in front end VLSI design

Complete Verilog HDL programming with Examples and Projects

What you'll learn

Explore related topics

Course content

Introduction to the course2 lectures • 36min

Introduction to Verilog HDL1 lecture • 29min

VLSI design flow ( FPGA & ASIC)2 lectures • 27min

Three levels of verilog design Description2 lectures • 6min

Verilog Language constructs, Data types & Compiler Directives3 lectures • 8min

Verilog Program structure4 lectures • 6min

Gate level modeling5 lectures • 6min

Data flow modeling14 lectures • 22min

Behavioral Modeling38 lectures • 1hr 30min

Switch level modeling1 lecture • 4min

Requirements

Description

Who this course is for: