Design & Verification using Verilog HDL +Project Demo

Name: Design & Verification using Verilog HDL +Project Demo
Rating: 4.3 (158 reviews)

ASIC Flow, Verilog Language, Digital Fundamentals, Combinational circuits, Sequential circuits, APB Protocol

Created byVLSI Mentor

Last updated 8/2026

English

English [Auto],

What you'll learn

ASIC Flow
Digital Fundamentals
Verilog constructs for design
Verilog constructs for verification
Memory design and verification
APB protocol learning

Course content

1 section • 10 lectures • 15h 57m total length

ASIC Flow - Architecture and RTL design verification2:03:48
Explore the Verilog and rtl driven ASIC flow from architecture to frontend design and functional verification, including test benches, synthesis, sta, and dft concepts.
ASIC Flow - Synthesis to GDS II1:39:52
Explore the Verilog design flow from synthesis to GDS II, including static timing analysis, gate-level simulation, DFT, scan insertion, ATPG, boundary scan, and physical design steps.
Hardware modeling using Verilog1:08:58
Cover Verilog hdls, modeling techniques, synthesis vs non-synthesis, and describe a four-to-one multiplexer with a flip-flop using modules, wires, regs, and testbenches; plus simulation steps from compilation to waveform verification.
Verilog Program Structure1:26:17
Explore Verilog program structure from Verilog 95 to SystemVerilog, covering modules, ports, wires and regs, synthesizable and non-synthesizable constructs, test benches, and basic logic gates.
Verilog Language constructs2:03:39
Explore Verilog language constructs, including modules, ports, wire and reg, procedural blocks, blocking and non-blocking assignments, sequential and combinational designs, memory arrays, and hierarchical design with testbenches.
Combinational Circuit design and Verification using Verilog1:40:33
Model combinational and sequential circuits in Verilog HDL, mastering multiplexers, encoders, decoders, and rtl synthesis for hardware blocks.
Sequential Circuit design and Verification using Verilog1:44:26
Master sequential circuit design in Verilog by building memory with flip-flops and registers, using clocks, resets, and test benches to verify edge-triggered behavior.
Timing and Event Scheduling1:51:39
Explore timing and event scheduling in Verilog HDL, covering setup and hold times, clock skew and jitter, metastability, and finite state machines with testbenches.
Projects and Simulations2:17:32
Explore Verilog HDL design and verification of memory and state machines, including asynchronous FIFO concepts, memory initialization, read_mem_h and write_mem_h utilities, and basic linting and CDC verification.
Lab and Project Assignment0:55

Requirements

Basics of Electronics
Linux commands

Description

The course basically for beginners to expert level in VLSI. The course covers in details about ASIC Flow, Verilog Language, Digital Fundamentals, Combinational circuits, Sequential circuits, APB Protocol.

It has 9 videos each more than 1 hr, with theory explanation and the hands on program execution.

Cadence Xcelium simulator used for Verilog program execution in linux Environment.

The programs are edited in vi editor.

The following are the course topics:

Session 1: ASIC Flow - Architecture, Design, RTL coding, Verification, DFT overview

Session 2: Synthesis, Static Timing Analysis, Physical Design, FPGA Emulation overview, Digital fundamentals

Session 3: Hardware modeling using Verilog

Session 4: Verilog Program Structure

Session 5 : Verilog Language constructs

Session 6: Combinational circuit design and verification using Verilog

Session 7: Sequential circuit design and verification using Verilog

Session 8: Timing and Event scheduling

Session 9: Projects : Memory design, FIFO and codes and simulations

This course is very good for those wants to do internship, want to learn and start career in VLSI. This helps for acquiring domain knowledge in VLSI and seek job in this industry. These basic concepts and language helps to attend interviews.

The course is designed and delivered by an ASIC Design and Verification Expert worked more than 2 decades in the Semiconductor Industry

Who this course is for:

For BE/BTech/MTech ECE/EEE students - who want to do Internship
ECE/EEE Engineers seeking career in VLSI industry