Design Verification with SystemVerilog/UVM

Explore APB agent infrastructure within a UVM testbench, focusing on the app agent, its interface and configuration component, and using the UVM configuration database to pass a virtual interface.

Learn to build an APB agent infrastructure: create the APB package, APB interface, and agent configuration, connect the interface via the UVM config db, and verify setup during simulation.

Explains the APB driving item in a UVM verification environment, with logic. Lists fields: direction, address, data, and the predictive and post-drive delays, noting inheritance from a UVM sequence item.

Implement the APB driving item in a UVM package by creating the item base and item drive classes with randomized direction, address, data, and pre/post drive delays.

Explore the UVM sequence mechanism, focusing on sequencer and driver interactions to drive APB transactions via APB item drive, sequences, and macros.

Implement the APB sequence mechanism by building the driver, sequencer, and three sequences: simple read, write, and random within a UVM APB agent, demonstrating do and send macros.

Implement a drive transaction task to place item drive information on the APB bus, and wrap it in a drive transactions loop with initialized signals for reset readiness.

Implement the apb driver logic by coding drive transaction and drive transactions, wiring the virtual interface via the agent configuration and driving apb signals.

This lecture presents the apb monitor inside the apb agent, collecting direction, address, and data from apb signals, selecting write or read data, and broadcasting via a uvm analysis port.

Implement the apb item mode and apb monitor in a uvm testbench, collecting direction, address, data, response, and length through a transaction output port.

Extract APB protocol checks from the APB documentation, asserting rules like p enabled timing, constant master signals, and no unknown values to validate APB behavior.

Implement APB protocol checks in a SystemVerilog/UVM workflow by adding synchronized fields, sequences, and assertions to verify p enable timing, stability, and transfer length via a monitor.

Develop APB coverage by extending a UVM component and using analysis port. Define tables for direction, response, length, address and data coverage with cover points, crosses, and a verification plan.

Learn to implement APB coverage with UVM, creating a coverage component, cover groups, and an analysis port to sample monitor data, with per-instance coverage and address/data wrappers.

Explore APB reset handling in the APB agent. Implement a reset handler interface and forever loops to restart driver, monitor, sequencer, and coverage when reset activates.

Learn to implement an APB reset handler across the agent, driver, sequencer, monitor, and coverage in SystemVerilog/UVM, handling asynchronous reset and start/end sequencing during APB accesses.

Consolidate your knowledge of the APB agent by reviewing its UVM architecture, driving items and sequences, and creating coverage and checks from the APB standard.

Explore the memory data protocol, a nonstandard md interface documented in the aligner specifications, featuring a 32-bit data bus and offset and size that define valid bytes and ready signals.

Explore the emd agent architecture with master and slave roles, using a common monitor and sequencer, and implement a parameterized data width with separate master and slave drivers.

Build the EMD agent infrastructure with master and slave adc/takes agents, a parameterized CFS MDIF interface, and UVM factory overrides including set instance override to tailor configs.

Build the MD agent infrastructure in a SystemVerilog/UVM workflow by creating the MD agent interface, agent config classes, and slave/master agents wired through the UVM config db.

Design the md master driving logic by shaping the item with data, offset, pre drive delay, and post drive delay, driving via the sequencer and driver.

Code the MD master driving logic in a UVM testbench, creating the MD item drive, master sequencer, and master driver, with soft and hard data constraints and a convert-to-string method.

Implement the MD monitor inside the MD agent using the UVM transaction API, capturing begin time and end time and streaming the MD item data through the output port.

Code the MD monitor in Verilog, add a type for the response and five fields, implement begin and end time handling, and verify with a collect transaction task.

Explore how the EMD slave driving logic uses item fields: length, response, and ready to model transactions, and how monitor-sequence synchronization via a UVM TLM FIFO refines driver timing.

Implement the MD slave driving logic by coding the item drive slave, slave driver, and sequencer with slave sequences, while updating the inheritance tree and test harness.

Explore MD protocol checks by deriving rules for signal behavior from aligner specifications, including 12 core rules and four extra rules, implemented as assertions and interface checks.

Develop and verify MD protocol checks across simulators, implementing all 16 rules, including data width power-of-two validation and active assertions.

Implement md coverage in the md agent using a verification plan, recording monitor data, crossing offset and size, and verifying data bit toggling across resets to support the md protocol.

Develop and adapt MD coverage for the MD protocol in a UVM environment, modeling offset, size, and reset coverage using the APB coverage as a reference.

Concludes the MD agent by identifying protocol rules from the aligner spec and implementing a master-slave RX/TX agent with inheritance, parameterization, width checks, and UVM transactions.

Discover the UVM extension agent configuration class with a parameterized virtual interface type and shared fields like active, passive, coverage, and checks.

Code the UVM extension agent config class, extend APB and MD configs, import the UVM extension package, and adapt getters, setters, and initialization for a successful simulation.

Explore the UVM extension monitor API shared by the APB and MD monitors, including common API, agent config, output port, and abstract collect transaction.

Practice implementing a UVM extension monitor by extending app and MD monitors, marking collect transaction as abstract, and connecting the agent config during elaboration for a clean simulation.

Explore UVM extension coverage by reusing wrapper classes for APB and MD protocols, implementing cover items and cover groups, and refining sample, reset handling, and report phase logic.

Code the UVM extension coverage class and adapt APB and MD packages to inherit it, wiring agent config pointers and enabling report-phase coverage printing in simulations.

Explore the UVM extension sequencer class, its inheritance from APB and MD packages, and how handle_reset becomes common, simplifying APB and MD code and removing cfs_apb_sequencer.

code the UVM extension sequencer class, declare the sequencer, move the handle_reset() function from the APB package, replace its usage, and verify compilation across the APB and MD packages.

Explore the UVM extension driver architecture, showing APB and MD drivers with a common API and distinct drive_transaction and handle_reset implementations.

Code the uvm extension driver by migrating apb driver APIs and having the md driver inherit it, using uvm_ext_reset_handler for reset handling. Validate via simulation to fix psel reset errors.

learn how to implement a uvm extension agent with a common api for apb and md, and configure it via the uvm configuration database.

Code the UVM extension agent class, adapt APB and MD agents to inherit from it, and enable TX agent configuration via the UVM configuration database, with selective overrides.

Explore the UVM extension package that consolidates repetitive code from APB and MD agents, reduces lines of code, and enables template-driven code generation for reusable verification components.

Explore the uvm register model to map the DUT registers via APB, including control, status, interrupt enable, and interrupt requests, using uvm_reg_field, uvm_reg_block, and uvm_reg_map for reads and writes.

Learn how to model UVM register fields with the uvm_reg_field class, including mirrored, desired, reset values, and access types; understand reserved fields and configure usage.

Implement the uvm register model by creating a uvm_reg subclass for four registers with public, rand fields named in uppercase, and a build() that calls configure() for each field.

Code four UVM register classes for the aligner rtl, including control, status, interrupt requests enable, and interrupt requests, defining fields like size, offset, clr, and rx/tx levels, with UVM_NO_COVERAGE.

Create a uvm_reg_block for the aligner by extending uvm_reg_block, declaring registers with rand attributes, and building an APB map with create_map and add_reg.

Code a UVM register block in a hands-on practice project, defining four registers and building the address map. Enable check-on-read and model the block in the UVM environment.

Integrate the register block with the apb bus monitor via the uvm_reg_predictor and a cfs_apb_reg_adapter, translating cfs_apb_item_mon to uvm_reg_bus_op for register updates and verification.

Learn to integrate the register model with the APB bus monitor by implementing a cfs_apb_reg_adapter, wiring a uvm_reg_predictor, and handling reset through a uvm_ext_reset_handler in a register access test.

Extend the uvm_reg_predictor to create a custom predictor that updates registers only on OK rtl responses, using the bus_in analysis port. Apply get_exp_response and aligner rules via environment config.

Implement a custom register predictor to filter APB writes with errors, validate responses, and guard control register writes by analyzing SIZE and OFFSET fields in the protocol.

Integrate the register block with the bus sequencer to use uvm_reg tasks for write, read, and update. Configure reg2bus and set_sequencer, and apply UVM constraints for controlled, randomized testing.

Integrate the register block with the APB bus sequencer by implementing reg2bus and bus2reg, connect the sequencer, and enforce SIZE and OFFSET constraints aligned to the aligner data width.

Implement a register field callback in SystemVerilog UVM by overriding post_predict() in a uvm_reg_cbs subclass and attaching it via uvm_callbacks to the predict() function of a uvm_reg_field.

Learn to implement a register field callback in systemverilog/uvm, clearing the cnt_drop drop count when the clr field writes, and validate with status reads and waveforms.

Learn to model registers with uvm_reg and uvm_reg_field, group them into a register model, and verify APB RTL data and responses using the uvm_reg read, write, and update methods.

See how the model generates the MD RX and TX outputs plus interrupt requests, while a scoreboard compares RTL and model results to catch mismatches with UVM errors.

Explore the model architecture for the aligner verification environment, detailing rx controller and fifo flow, alignment logic, and tx controller interactions with the tx fifo and the scoreboard.

Define and instantiate the model interface, including input and output UVM analysis ports for RX and TX, implement write() methods, and connect data via port_out_rx and port_out_tx to the scoreboard.

Implement the model interface by declaring uvm analysis classes for two input ports (rx, tx) and three output ports, wiring cfs_md_item_mon and cfs_md_response, and connecting ports in the environment.

Model illegal RX accesses in the RX controller by incrementing CNT_DROP and signaling MAX_DROP at 255, with RX monitor inputs and enabling interrupts, using get_exp_response, set_max_drop, inc_cnt_drop, and write_in_rx.

Learn to model illegal rx accesses in systemverilog/uvm by implementing get_exp_response, set_max_drop, and inc_cnt_drop, and integrating them from write_in_rx in a random test scenario.

Model legal RX accesses by detailing an RX FIFO based on the UVM TLM FIFO, tracking RX_LVL and RX_FIFO_FULL with sticky interrupts and a non-blocking push to the RX FIFO.

Model legal rx accesses by implementing an rx fifo with uvm_tlm_fifo of cfs_md_item_mon, track rx_lvl and rx_fifo_full, and verify with a random test.

Model the intermediate buffer logic in SystemVerilog/UVM by simulating RX_LVL and RX_FIFO_EMPTY behavior, including pop_from_rx_fifo, build_buffer, alignment logic, and API updates with a clock interface and environment config.

Set up and simulate intermediate buffer model by defining a virtual interface, adding the buffer API to the model, and exercising rx fifo push and pop flows in a testbench.

Model the align logic to pop data from the intermediate buffer, align it, and push to the TX_FIFO, while updating TX_LVL and TX_FIFO_FULL and implementing split, align, and push_to_tx_fifo APIs.

Implement the align logic in a SystemVerilog/UVM model by building and pushing to the TX FIFO, mirroring the RX FIFO, and validating alignment with control registers and log messages.

Model the TX controller logic by popping from the TX FIFO, updating TX_LVL and TX_FIFO_EMPTY flag, and signaling completion with a uvm_event to synchronize with the MD TX interface.

Implement the model TX controller in SystemVerilog/UVM by adding TX FIFO management, TX level counters, the tx_complete event, and the tx_ctrl task to drive verification against scoreboard.

Explore the scoreboard architecture in the verification environment, verifying RTL outputs against model-generated expected data for MD RX, MD TX, and interrupt requests, using queues and timers to enforce checks.

Declare the scoreboard as a uvm_component with reset handler, and define ports for model rx/tx data and irq (cfs_md_response, cfs_md_item_mon), plus agent rx/tx ports and an rtl interrupt via environment.

Code the scoreboard interface in a UVM environment by declaring the scoreboard class and analysis ports. Instantiate in build_phase and connect_phase to wire model and agents ports with reset handling.

Explore implementing a scoreboard check for the rx response in systemverilog uvm, using ports port_in_model_rx and port_in_agent_rx, an exp_rx_responses queue, and a watchdog with a configurable threshold.

Implement an RX response scoreboard check in SystemVerilog/UVM by adding an expected rx responses queue, a watchdog with a threshold from environment config, and compare received versus expected responses.

Implement the TX item scoreboard check by wiring ports port_in_model_tx and port_in_agent_tx, maintaining the exp_tx_items queue of cfs_md_item_mon, and using a watchdog with a ten cycle threshold.

Implement the TX item scoreboard check by adding an expected TX items queue, a TX watchdog, and a 10 threshold, and validate TX data, size, and offset.

Implement an interrupt request scoreboard check in the scoreboard class, featuring a queue of expected interrupt requests and process pointers, a watchdog task, and the rcv_irq mechanism for dut monitoring.

Learn to implement the scoreboard check for interrupt requests in a SystemVerilog/UVM environment by adding APIs, queues, threshold handling, and irq/reset signals, plus testbench integration and debugging tips.

Learn how to synchronize rx and tx fifo flags in a SystemVerilog/UVM model using process pointers and kill functions to cancel empty/full flag updates during simultaneous push and pop.

Fix synchronization of FIFO flags in the model by adding process pointers, kill functions, and updated push and pop tasks, aligning with RTL behavior and preventing RX_FIFO_EMPTY interrupts.

Learn to fix push and pop synchronization between a model and RTL by implementing synchronization tasks using fork-join_any, probing RX and TX fifo events, keeping RX and TX fifo states.

Implement push and pop synchronization by probing rtl signals, adding synchronization tasks, and updating the push and pop actions; validate with simulation, waveforms, and an updated uvm scoreboard.

Learn to resolve model synchronization issues from overlapping interrupt requests by implementing an or gate behavior with a local exp_irq, a send_exp_irq task, and synchronized scoreboard updates for systemverilog/uvm.

Fix the model synchronization issue with overlapping irq requests by adding an exp_irq field and updating reset logic and the send_exp_irq task to ensure one interrupt is sent and checked.

Learn how to implement DUT functional coverage within a verification environment by building a spec-based verification plan, creating a coverage component, and covering split functionality with cross analyses.

Implement DUT functional coverage by adding a split information class and a coverage component. Connect the model and environment to collect, sample, and report split coverage during build and run.

Extend uvm_sequencer to create a virtual sequencer and reference MD RX, MD TX, and APB sequencers. Coordinate RX and TX across interfaces with virtual sequences using uvm_do_on and uvm_do_on_with.

Design and implement a virtual sequencer in uvm, wiring md rx/tx sequencers and a base virtual sequence, then run a slow pace sequence to drive rx and tx transactions.

Master how to model a DUT's behavior, verify outputs, and tackle synchronization issues with process pointers and internal probing, while building functional coverage and reusable virtual sequences.

Learn debugging and testing in design verification with SystemVerilog/UVM, including running regressions and three debug techniques using UVM messages, transactions, and organized tests to pinpoint failures.

Explore how to control and filter uvm messages with the uvm_info macro, set verbosity using +uvm_set_verbosity, and organize IDs for effective debugging in UVM environments.

Learn to implement and filter the UVM message system for debugging. Update message IDs and verbosity, add a messages.f file, and filter by rx_fifo and item_end.

Learn to visualize waveforms with UVM transactions, using bubbles to show APB/MD data, and configure recording via uvm_recorder and UVM_FULL.

Apply the 'track the source' debugging technique to trace mismatches from MD RX transactions through RTL and the environment, using a mon2env adapter and a sources queue.

Organize UVM tests by using a single random test and inheritance to constrain traffic, targeting features such as the drop counter and RX/TX FIFOs with virtual sequences.

Cristian Slav demonstrates randomization of the register access test, using fork-join branches for random and unmapped APB accesses driven by configurable counts.

Implement and run randomized register access tests in design verification with systemverilog/uvm, using two parallel sequences—randomized mapped accesses and unmapped address accesses—via the run_phase.

Design verification with systemverilog/uvm shows updating a random traffic test to write config registers, send random md rx traffic, and read status registers using virtual sequences.

Enhance the random traffic test with three virtual sequences to write random values to configuration registers, read status registers, and send a single random md rx transaction.

Extend random test with a constraint-driven virtual sequence to generate only illegal rx traffic, using aligner data width and pre_randomize; drive 300 md rx transactions to saturate the drop counter.

Implement an illegal rx traffic test with a virtual sequence, constrain illegal rx transactions, and validate rtl interrupt behavior by setting 300 md rx transactions.

Build a verification environment from scratch and learn to control uvm messages and transactions for debugging, organize tests with inheritance, and create random and constrained tests that reveal rtl bugs.

Explore the stages of a verification project, from understanding DUT specifications with concept engineers to building a verification environment, conducting reviews, running regressions, and achieving 100% coverage and sign-off.

Complete the design verification course by mastering reusable UVM agents, DUT and register modeling with the UVM library, callbacks and randomization, plus debugging, synchronization, and a 5000-line final project.