Design Verification with SystemVerilog/UVM

Explains the APB driving item in a UVM verification environment, with logic. Lists fields: direction, address, data, and the predictive and post-drive delays, noting inheritance from a UVM sequence item.

Implement the APB driving item in a UVM package by creating the item base and item drive classes with randomized direction, address, data, and pre/post drive delays.

Implement a drive transaction task to place item drive information on the APB bus, and wrap it in a drive transactions loop with initialized signals for reset readiness.

Consolidate your knowledge of the APB agent by reviewing its UVM architecture, driving items and sequences, and creating coverage and checks from the APB standard.

Code the MD master driving logic in a UVM testbench, creating the MD item drive, master sequencer, and master driver, with soft and hard data constraints and a convert-to-string method.

Explore how the EMD slave driving logic uses item fields: length, response, and ready to model transactions, and how monitor-sequence synchronization via a UVM TLM FIFO refines driver timing.

Implement the MD slave driving logic by coding the item drive slave, slave driver, and sequencer with slave sequences, while updating the inheritance tree and test harness.

Code the UVM extension agent config class, extend APB and MD configs, import the UVM extension package, and adapt getters, setters, and initialization for a successful simulation.

Explore the UVM extension monitor API shared by the APB and MD monitors, including common API, agent config, output port, and abstract collect transaction.

Explore UVM extension coverage by reusing wrapper classes for APB and MD protocols, implementing cover items and cover groups, and refining sample, reset handling, and report phase logic.

Explore the UVM extension sequencer class, its inheritance from APB and MD packages, and how handle_reset becomes common, simplifying APB and MD code and removing cfs_apb_sequencer.

Explore the UVM extension driver architecture, showing APB and MD drivers with a common API and distinct drive_transaction and handle_reset implementations.

Learn how to model UVM register fields with the uvm_reg_field class, including mirrored, desired, reset values, and access types; understand reserved fields and configure usage.

Implement the uvm register model by creating a uvm_reg subclass for four registers with public, rand fields named in uppercase, and a build() that calls configure() for each field.

Code a UVM register block in a hands-on practice project, defining four registers and building the address map. Enable check-on-read and model the block in the UVM environment.

Learn to integrate the register model with the APB bus monitor by implementing a cfs_apb_reg_adapter, wiring a uvm_reg_predictor, and handling reset through a uvm_ext_reset_handler in a register access test.

Implement a custom register predictor to filter APB writes with errors, validate responses, and guard control register writes by analyzing SIZE and OFFSET fields in the protocol.

Integrate the register block with the APB bus sequencer by implementing reg2bus and bus2reg, connect the sequencer, and enforce SIZE and OFFSET constraints aligned to the aligner data width.

Implement a register field callback in SystemVerilog UVM by overriding post_predict() in a uvm_reg_cbs subclass and attaching it via uvm_callbacks to the predict() function of a uvm_reg_field.

See how the model generates the MD RX and TX outputs plus interrupt requests, while a scoreboard compares RTL and model results to catch mismatches with UVM errors.

Define and instantiate the model interface, including input and output UVM analysis ports for RX and TX, implement write() methods, and connect data via port_out_rx and port_out_tx to the scoreboard.

Implement the model interface by declaring uvm analysis classes for two input ports (rx, tx) and three output ports, wiring cfs_md_item_mon and cfs_md_response, and connecting ports in the environment.

Model legal rx accesses by implementing an rx fifo with uvm_tlm_fifo of cfs_md_item_mon, track rx_lvl and rx_fifo_full, and verify with a random test.

Implement the align logic in a SystemVerilog/UVM model by building and pushing to the TX FIFO, mirroring the RX FIFO, and validating alignment with control registers and log messages.

Declare the scoreboard as a uvm_component with reset handler, and define ports for model rx/tx data and irq (cfs_md_response, cfs_md_item_mon), plus agent rx/tx ports and an rtl interrupt via environment.

Implement the TX item scoreboard check by wiring ports port_in_model_tx and port_in_agent_tx, maintaining the exp_tx_items queue of cfs_md_item_mon, and using a watchdog with a ten cycle threshold.

Learn how to synchronize rx and tx fifo flags in a SystemVerilog/UVM model using process pointers and kill functions to cancel empty/full flag updates during simultaneous push and pop.

Fix synchronization of FIFO flags in the model by adding process pointers, kill functions, and updated push and pop tasks, aligning with RTL behavior and preventing RX_FIFO_EMPTY interrupts.

Implement push and pop synchronization by probing rtl signals, adding synchronization tasks, and updating the push and pop actions; validate with simulation, waveforms, and an updated uvm scoreboard.

Learn to resolve model synchronization issues from overlapping interrupt requests by implementing an or gate behavior with a local exp_irq, a send_exp_irq task, and synchronized scoreboard updates for systemverilog/uvm.

Learn to implement and filter the UVM message system for debugging. Update message IDs and verbosity, add a messages.f file, and filter by rx_fifo and item_end.

Learn to visualize waveforms with UVM transactions, using bubbles to show APB/MD data, and configure recording via uvm_recorder and UVM_FULL.

Cristian Slav demonstrates randomization of the register access test, using fork-join branches for random and unmapped APB accesses driven by configurable counts.

Enhance the random traffic test with three virtual sequences to write random values to configuration registers, read status registers, and send a single random md rx transaction.

Complete the design verification course by mastering reusable UVM agents, DUT and register modeling with the UVM library, callbacks and randomization, plus debugging, synchronization, and a 5000-line final project.