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BCH (15,11,1) algorithm With VHDL
Rating: 3.9 out of 5(6 ratings)
14 students

BCH (15,11,1) algorithm With VHDL

VHDL Code of BCH (15,11,1) algorithm
Created byAmr Ahmed
Last updated 7/2022
English
English

What you'll learn

  • Define the coding theory
  • Define the Bose–Chaudhuri–Hocquenghem (BCH) codes
  • Define the types of BCH codes
  • Explain the BCH (15,11,1) encoder with VHDL
  • Explain the BCH (15,11,1) decoder with VHDL

Course content

1 section • 5 lectures • 30m total length

  • Introduction of Coding theory5:29

    Explore coding theory in the BCH algorithm course, explaining how noise alters data bits and how party bits form code words to detect and correct errors.

  • The BCH and its types1:47

    Explore the BCH code, cyclic codes with a feedback shift register encoder, and define X, Y, and Z as code word, message bits, and detectable errors in VHDL.

  • The BCH (15,11,1) encoder with VHDL5:52

    explains how the BCH (15,11,1) encoder with VHDL converts 11-bit messages into 15-bit codewords using a four-parity-bit scheme implemented with shift registers.

  • The BCH (15,11,1) decoder with VHDL7:24

    Understand the BCH (15,11,1) decoder with VHDL, deriving the message polynomial and computing the syndrome. Analyze constructing and inverting the M matrix, locate the error, and simulate correction.

  • Practical Examples with VHDL9:59

    Explore three practical examples of encoding and decoding using the BCH (15,11,1) algorithm with VHDL.

Requirements

  • Basic Understanding of telecommunication.
  • Basic Understanding of Digital Logic Gates.
  • Xilinx ISE Design Suite 14.7 Software.

Description


  • The course contains some lectures that explain in detail the Bose–Chaudhuri–Hocquenghem codes (15,11,1) algorithm used for error detection and correction. the number 15 is referring to the total transmitted message bit size, 11 is the information bit size, and 1 is the number of errors that can be detected and corrected.

  • the course contains a VHDL code for the algorithm that is attached to the lectures that you can download and use it.

  • This course targets the VHDL code and the FPGA implementation of this algorithm. it will be helpful for the undergraduate engineering students and the postgraduate also.

  • the VHDL codes are not easy to be valid on the websites so it is difficult to find the VHDL code for a certain project that works correctly but in this course, the full VHDL code will be available with its test bench so you can download and adjust it as you want.

  • You will learn by doing real VHDL programming. All the code and syntax are attached. After you adjust the existing code or you create your own, you will run simulations to verify it. If you are interested to run your code on real hardware (not required, but much more fun), we recommend Altera or Xilinx boards.

Who this course is for:

  • The communication Engineers.
  • The Engineering Undergraduate and Postgraduate Students.
  • Digital Circuits Designers.
  • The Test Engineers.
  • The Engineering Project Manager.
  • The System Engineers.
  • The Embedded System Engineers.
  • Individuals pursuing Electrical Engineering
  • Anyone interested to learn Xilinx FPGA/ Vivado Design Suite/ VHDL Hardware Description Language

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