Baremetal programming esentials for the AMD Zynq-7000 SoC

Name: Baremetal programming esentials for the AMD Zynq-7000 SoC
Rating: 4.8 (2 reviews)

FPGA Zynq baremetal ARM

Created byMaryam del Mar Correa Gómez

Last updated 6/2026

English

What you'll learn

Clarity about the digital architecture proposed by AMD for baremetal application development
Clearly distinguish the elements that make up AMD’s proposed PL‑PS system
Understand the steps involved in the Zynq SoC bootloader execution process
Acquire a basic understanding of AXI‑4 interface interconnections
Use Vivado and Vitis to develop baremetal programming projects
Understand how to navigate the standalone peripheral‑driver documentation
Know how to create block designs manually and understand Vivado’s automatic connection features
Correctly use pointers to peripheral‑instance structures
Understand how to profile any function with execution times of 1 microsecond or longer
Understand how to initialize driver instances
Use the graphical debug mode and gain an initial introduction to command‑line debugging using the XSDB tool
Work with various GPIO I/O types: buttons, switches, LEDs, RGB LEDs, and header pins
Use the default and automatic sequencer modes of operation from the XADC peripheral
Perform data acquisition using the XADC, the DMA, and external DDR3 RAM
Use the I2C protocol via the IicPs and XIic drivers
Foundations of the SoC’s interrupts, timers, watchdogs and resets
Add a baremetal application to the FSBL bootloader, to create a boot image stored in Flash memory

Course content

9 sections • 58 lectures • 6h 22m total length

Excerpt 11:29
Excerpt 21:52
Build the block diagram by adding key IP cores: Zynq processor, processor system reset, AXI direct memory access, AXI4-Stream subset converter, XADC, AXI interconnects, AXI GPIO.
Excerpt 30:38
Implement two high-level gpio configuration functions for single or dual channel gpio, initialize with XGpio_Initialize() with the correct parameters, check status, run XGpio_SelfTest(), and set data direction.
Excerpt 41:11
Experiment with prepped color combinations to reveal vibrant, dynamic RGB LEDs while running the project, and explore your own color variations for further possibilities.
Excerpt 51:31

Why baremetal is important even in the age of Linux builds and RTOSes?1:33
Intro1:07
Master baremetal programming for the AMD Zynq-7000 SoC using the standalone driver set with no prior knowledge. Learn essential concepts, practical examples, and the architecture for baremetal and Linux programming.
Overview24:50
FPGA Veterans - What has changed?20:16
Discover how AMD's Vivado and Vitis HLS streamline FPGA development with high-level synthesis and IP-based design, enabling timing closure, IP reuse, and block design across 7-series, Ultrascale+, and Versal devices.
Architecture for baremetal and Linux programming10:41
Explore a layered bare-metal and Linux programming architecture for the Zynq-7000 SoC, using a portable, OS-neutral driver model across RTOS adapters, including FSBL, clocks, DDR, and secure-boot options.
Test your understanding

GPIO - Theory7:52
Preparation for the practical projects0:43
GPIO - Vivado hardware platform16:16
GPIO - Vitis peripheral initialization9:36
GPIO - Low level functions3:13
GPIO - Elaborating custom delays and Custom time profiling of functions13:40
Define custom delay functions and integrate xiltimer to access the global timer for precise delays, then measure and profile function times using inline assembly no-ops and PMU or AXI monitoring.
GPIO - High level functions11:43
Explore high-level AXI GPIO functions to read buttons and switches on the Zynq-7000, organizing code into header, c, and main files, with initialization, data direction, and 10 ms polling.
GPIO - Buttons and switches2:35
Debouncing of inputs1:55
GPIO - Outer header2:44
GPIO - RGB LEDs5:53
Demonstrates a basic rgb led control function with pwm, duty cycle validation (0–50%), and 0–500 microseconds timing, mapping red, green, and blue channels to gpio bits in a vivado project.

XADC- Theory7:18
Explore the zynq-7000 xadc peripheral, featuring 12-bit resolution at 1 msps and 2 lsb integral non-linearity, with 1 mv accuracy and 17 analog input channels, via ps and axi interconnect.
XADC, Default mode - Vivado hardware platform9:16
Builds a Vivado hardware platform for a Zynq-7000 with an XADC instance, selects the single-channel mode and calibration, then exports hardware to Vitis for a bare-metal XADC application.
XADC - Vitis peripheral initialization10:43
Initialize the XADC peripheral on the AMD Zynq-7000 by generating the XSA, configuring with XAdcPs_LookupConfig and XAdcPs_CfgInitialize, running a self-test, and confirming the PS base address 0xF8007100.
XADC, Default mode - Vitis application project2:57
XADC, Continuous sequencer mode - Vivado hardware platform6:42
Preparation of analog custom inputs0:23
XADC, Continuous sequencer mode - Vitis application project8:15
Set up the workspace, hardware platform, and Vitis project; enable safe mode and continuous sequencer mode for six-channel XADC sampling, then read and convert data, and monitor LM35 temperature.
Solving discrepancies between analog readings3:22
Simple SoC temperature control - Vivado hardware platform4:01
Build a Vivado hardware platform for simple temperature control by reading the on-chip temperature via XADC and driving a cooling fan through AXI GPIO on the Arty Z7 board.
Simple SoC temperature control - Vitis application project15:23
Implement an on-off temperature control loop in a Vitis project, reading XADC temperatures, comparing to a user-defined limit, and driving a fan via GPIO with a timer and PWM.

An introduction to AXI DMA and other DMA resources0:11
AXI DMA - Vivado hardware platform18:55
AXI DMA - Configuration and initialization in Vitis18:42
Initialize the AXI DMA in Vitis by configuring the device ID, memory base, and burst size, while setting up ping-pong buffers to overlap DMA transfers with processing.
AXI DMA - Analyzing a single databeat using the software debug perspective11:16
AXI DMA - Data acquisition of a capacitor discharge waveform16:37

Making I2C work in FPGAs13:05
Invitation to reading more about the I2C bus and its standards0:47
If this video clarified why I2C can be deceptively hard (especially in programmable logic) the next natural step is to strengthen your intuition of how the protocol really behaves on the wire. A Basic Guide to I2C is an excellent follow-up read. For junior engineers, it builds a clean mental model of SDA/SCL behavior, ACK/NACK phases, pull-ups, rise times, and clock stretching. For mid and senior engineers, it’s a surprisingly effective refresher: many of the “gotchas” that break real designs are explained clearly, with waveforms and electrical context that directly relate to the issues discussed in this video.

Once you’re comfortable with the concepts, there is no substitute for going to the source. The Philips I2C Bus Specification, now maintained by NXP Semiconductors, is not just a formal document: it’s institutional knowledge. This is where details like clock stretching rules, arbitration, timing constraints, and electrical limits are defined precisely. Many real-world bugs only make sense once you’ve seen how the protocol is supposed to behave according to the spec. Treat this document not as optional reading, but as a long-term reference you’ll come back to whenever an I2C bus behaves “mysteriously.”
I2CPS Hardware configuration in Vivado3:07
I2C Communications with the IicPs and AXI IIC software drivers0:29
I2C Scanner7:43
Learn to run a minimal I2C scanner on the AMD Zynq-7000 SoC to verify wiring, pull-ups, and driver setup before working with devices like ADS1115 and MAX30102.
Coding a custom driver for the ADS1115 ADC10:01
Handling repeated starts0:41
Using the AXI IIC driver with high and low level functions (plus Vitis Classic)8:44
An introduction to solving discrepancies in hardware handoffs0:56
IicPs and AXI IIC: what works, what doesn't and why5:40
Compare axi iic and iicps and learn safe i2c transaction patterns, including repeated start, stop, and timeouts, plus memory address mapping and hardware-to-software handoff in vivado and vitis.

Overview of timing and recovery resources32:50
Interrupts example 10:29
Interrupts example 20:34
XScu Timer, TTCPS timer and Watchdogs - Vivado hardware platform1:19
XSCU timer example0:10
TTCPS hardware-generated PWM output0:26
TTCPS timer - Software example0:26
Private watchdog (AWDT) example0:43
Using the MLX90393 sensor in burst operating mode17:03
Explore configuring and using the mlx90393 magnetometer in burst mode over i2c, including repeated starts and interrupt signaling data, and interpreting 3-axis magnetic field signatures for orientation and position detection.

Requirements

Having a board that has the AMD Zynq-7000 SoC, like: Digilent Arty Z7, Pynq Z1, Zybo, Zedboard, Eclypse; Avnet Microzed and AMD ZC702
Knowledge of theory and implementation of digital electronics, regarding combinatorial logic and sequential logic, either with VHDL or Verilog
Basic previous experience at programming microcontrollers and microprocessors. Doesn't matter if you come from programming with Arduino IDE or platformio in VSCode. You'll learn a lot here!

Description

Baremetal applications run without an OS, i.e. a scheduler or virtual memory, so your code’s behavior is fully determined by what you write. This makes them ideal when “missing a time deadline” is unacceptable.

Learning baremetal programming on the Zynq-7000 SoC is the foundation for deterministic, high-performance, and deeply understood AMD embedded systems that use the PS-PL platforms.

Learning to program at the standalone (baremetal) level on the PS helps you understand the PS–PL interconnect, AXI protocols, and driver design before layering on an OS.

In addition, the resulting codes between C and C++, as well as standalone and Linux builds, are similar between them.

Other reasons for taking this course:

In this course, you’ll get verified, clearly explained, and accurate code that works for this SoC.
Tired of unanswered forum questions? I’ve gathered some of the most common pitfalls and answered them here.
Every project done on this course is broken down step-by-step, guided by both the official documentation and my real-world experience.
It’s the very hands-on, practical course I wish I had seen around when I first got my Arty Z7 board.

Join me on this baremetal journey with the AMD Zynq-7000 SoC. Enroll now and build something amazing!

Who this course is for:

Undergraduate students familiar with FPGA basics but new to ARM Cortex processors
FPGA Hobbyists who want to master the standalone library and drivers
Young FPGA developers weighing their niche
FPGA veterans transitioning from legacy Xilinx tools
IP design and verification engineers who want to learn how to use AMD Zynq SoCs
Embedded systems engineers who see in FPGAs a tool to achieve a deeper understanding of the field

Baremetal programming esentials for the AMD Zynq-7000 SoC

What you'll learn

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Course content

Excerpts5 lectures • 7min

Zynq-7000 SoC Overview5 lectures • 58min

GPIO11 lectures • 1hr 16min

XADC10 lectures • 1hr 8min

DMA5 lectures • 1hr 6min

I2C10 lectures • 51min

Timing and recovery resources9 lectures • 54min

Flash memory1 lecture • 1min

Conclusion2 lectures • 2min

Requirements

Description

Who this course is for: