VLSI Digital Design using VHDL and Hardware:Handson
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VLSI Digital Design using VHDL and Hardware:Handson

A Complete RTL Package
0.0 (0 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
22 students enrolled
Last updated 4/2017
English
Current price: $10 Original price: $95 Discount: 89% off
5 hours left at this price!
30-Day Money-Back Guarantee
Includes:
  • 10.5 hours on-demand video
  • 26 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • After the course students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. and  Gain a strong foundation in VHDL RTL and test bench coding techniques.  Write VHDL RTL hardware designs using good coding practices.  Learn the synthesizable subset of VHDL.  Use types, overloading, and conversion functions from standard VHDL packages (std_logic_1164).  Distinguish coding for synthesis versus coding for simulation.  Know about VHDL constructs used in simulation and synthesis environments.  Write VHDL Bench s for simulation.  Target and optimize Xilinx FPGAs by using VHDL.  Run a timing simulation by using Xilinx ISim libraries.  Create and manage designs within the Xilinx Design Suite.  Correctly model combinational and sequential hardware blocks.  Write User constraints files for any FPGA board.
View Curriculum
Requirements
  • Basic digital design knowledge
Description

 

Course Description:

This course is a thorough introduction to the VHDL language. VHDL (VHSIC Hardware Description Language) is a versatile and powerful hardware description language which is used for modeling electronic systems at different levels of design abstraction.  This provides a foundation in RTL and test bench coding styles needed by design and verification engineers who are new to VHDL. This Sessions addresses targeting Xilinx FPGA devices to make sure you understand the whole process from simulation to FPGA. There is a lecture section for each main topic.  Lectures contain numerous examples that show both syntax and coding style. This presents a basic foundation for the language. The Knowledge gained can be applied to any digital design by using a top-down or Bottom-up synthesis design approach. This course combines lectures with lab exercises to strengthen key concepts.

Objective:

The Main goal of this course is give you an overview of the VHDL language and its use in logic designing including VHDL syntax , build models using language constructs such as assignment, process statements, if statements, case statements and loops and coding styles . To make you familiar with developing a RTL VHDL model to understand the synthesizable subset of VHDL and writing a verification test cases and User constraints files for that model.

 

Who should take this course?

This course is designed for designers who are new to VHDL and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. And Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs. 

 

 

At the end of the course, students will be able to:

After the course students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. and

  • Gain a strong foundation in VHDL RTL and test bench coding techniques.
  • Write VHDL RTL hardware designs using good coding practices.
  • Learn the synthesizable subset of VHDL.
  • Use types, overloading, and conversion functions from standard VHDL packages (std_logic_1164).
  • Distinguish coding for synthesis versus coding for simulation.
  • Know about VHDL constructs used in simulation and synthesis environments.
  • Write VHDL Bench s for simulation.
  • Target and optimize Xilinx FPGAs by using VHDL.
  • Run a timing simulation by using Xilinx  ISim  libraries.
  • Create and manage designs within the Xilinx Design Suite.
  • Correctly model combinational and sequential hardware blocks.
  • Write User constraints files for any FPGA board.

 

What will students need to know or do before starting the course? :

  • Basic digital design knowledge

Software Tools

  • Download the Xilinx ISE Design suite 14.4 System Edition and Install In to your System.
  • Digilent NEXYS 2 Board   WITH Spartan 3E -500E or 1200 E .

Hardware

  • Digilent NEXYS 2 Board   WITH Spartan 3E -500E or 1200 E .

Who is the target audience?
  • This course is designed for designers who are new to VHDL and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. And Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs.
Compare to Other VHDL Courses
Curriculum For This Course
70 Lectures
10:26:34
+
Introduction To VHDL
9 Lectures 01:46:42

VHDL_introduction_2(continuation) : Stracture of VHDL,Syntax for Entity
13:27


VHDL_libraries : source library,Work library,Rules for Identifiers
10:22

VHDL Operators :Logical and Bit wise operators,Shift Operators
09:06

VHDL Operators(Continuation):Arithmetic Operators,STD_Logic Operators
12:52

VHDL Data Types :VHDL DataType Object,constant,variable
15:23

VHDL DataTypes(Continuation) :VHDL DataType Signal,Delays,Values
13:41

VHDL_loops :assignments,blocks,Conditional Statements(IF - Else,Case),Loops
14:32
+
Number Systems
3 Lectures 41:12
Number Systems :Definition and Radix conversion
12:53

Number Systems :Weighted codes, Non weighted Codes
18:14

Number Systems: Gray Code, Gray Code Conversion, Error Detection Codes
10:05
+
Logic gates
5 Lectures 01:06:32
Logic Gates: Theory: Logic gates_Introduction,Basic gates
18:05

Logic Gates: Theory: Special pupose gates
10:39

Logic Gates: Program
08:34

Logic gates Program (Continuation)
16:23

Logic Gates: Hardware
12:51
+
Digital design Combinational
26 Lectures 03:18:53
Multiplexer : Theory
07:16

Multiplexer : Program
15:28

Multiplexer : Hardware
05:24

Demultiplexer
06:11

Encoders : Theory
07:20

Encoders : Program
11:26

Encoder : Hardware
06:56

Priority Encoders: Theory
07:13

Decoders : Theory (Part 1)
05:51

Decoders : Theory (Part 2)
04:35

Decoders : Program
14:22

Decoders : Hardware
03:36

Comparators : Theory
05:43

Comparators : Program
10:18

Comparators : Hardware
08:52

Majority Gate : Program
07:37

Majority Gate: Hardware
03:15

Arithmatic Circuits: Half Adder Theory
07:13

Arithmetic Circuits: Half Adder Program
09:02

Arithmatic Circuits: Full Adder Theory
10:31

Arithmatic Circuits: Ripple Carry Adder Theory
05:16

Arithmatic Circuits: Ripple Carry Adder Program
11:27

Arithmatic Circuits: Ripple Carry Adder Hardware
04:58

Arithmatic Circuits: Universal Ripple Carry Adder Theory
06:18

Code Converters : bin to gray program
08:45

Code Converters : bin to gray Hardware
04:00
+
Digital design Sequential
27 Lectures 03:33:15
Sequntial Circuits _theory
06:00

Flip Flops & Latches: SR Flip Flop Theory
16:32

Flip Flops & Latches: JK Flip Flop Theory
10:05

Flip Flops & Latches: JK Flip Flop Program
10:41

Flip Flops & Latches: JK Flip Flop Hardware
04:20

Flip Flops & Latches: D Flip Flop Theory
08:39

Flip Flops & Latches: D Flip Flop Program
09:40

Flip Flops & Latches: D Flip Flop Hardware
02:24

Registers : Theory
12:34

Registers: SISO Theory
25:32

Registers : SISO Program
12:58

Registers : SISO Hardware
02:03

Registers : SIPO Theory
07:52

Registers : SIPO Program
08:30

Registers : SIPO Hardware
01:37

Registers : PIPO Theory
05:04

Registers : PIPO Program
10:38

Registers : PIPO Hardware
03:15

Counters: Jhonson Counter Theory
05:32

Counters: Jhonson Counter Program
07:57

Counters: Jhonson Counter Hardware
01:59

Counters: RING Counter Theory
08:00

Counters: RING Counter Program
08:40

Counters: RING Counter Hardware
01:59

Programming of BASYS 3 board with Vivado
13:53

Programming of BASYS 3 board with Vivado_hardware
03:05

talking head video to verification : hassan@iblocks.in
03:46
About the Instructor
Hassan Uddin Shaik
3.1 Average rating
30 Reviews
227 Students
3 Courses
Learn from the LEADER

I, Hassan Uddin Shaik, having vast experience in the field of Embedded Systems and VLSI. I have 8+ Years’ experience and worked in major fields of Embedded Systems and VLSI.

Programming Languages known: Assembly, C, C++, JAVA, J2ME

Database: MS-Access, ORACLE

ScriptingLanguages: HTML, PHP

OperatingSystems: DOS, UNIX, WINDOWS, LINUX, FreeRTOS, MicroCOS-III.

HardwareKnowledge: Knowledge of hardware components, Networking and Embedded Systems.

Microcontrollers: ARMCortexM3–LPC1768, TI-LM3S89, STM32, ADE7xxx (Analog Devices), ARM7TDMI–LPC2148, MSP430x42x(Texas Instruments), AT89S51, Atmega, PIC18F, Xmega, FPGASpartan

IDE: Kiel, IAR, Atmega(AVR)studio, Mplab-x

Tools: COMSOL, L-Edit, SUPREME, CASINO, ACESSimulations, SPIP, BSIM, NGSPICE, PSPICE, MOSES1.2,

Microtek (Simulating Software), Synopsys, Cadence, SOC Encounter, Xilinx

EducationProfile: Ph.D : Pursuing at Jodhpur National University (expected to finish by January 2016); M.S-MicroNanoFabrication from DTU (Denmark Technical University-Denmark); M.Tech– Nano Electronics from VIT University (Vellore– Tamilnadu); B.Tech–Electronics and Communications from DVRCET–JNTUH.

ResearchProfile: ResearchFellow at KTH–Sweden(2 months), Research Fellow at UTO(University of Oldenberg)–Germany (2 months); Research Fellow at EPFL–Zurich (2 months); Research Fellow at JNCASR (IISC -Bangalore); Research Assistant at UUM (Universiti Utara Malaysia)

Journals: Nano bits: customizable scanning probe tips

Published in – IOP Nanotechnology