>>>Latest !!! we also have attached "Reference Guide on VHDL Programming with this Course"<<<
This Course is of VHDL Programming from Basic (logic gate design) to Advance Design (Structural Design and State Machine Design). After completing the course student will get idea of VHDL programming design methodology, VIVADO Design Flow, Zynq Architecture, Creating Simulation Testbench, Conditional Statements, Combinational Circuit Design with VHDl, Sequential Circuit Design, Structural Design in VHDL and State Machine Design in VHDL.
In each section we have included Lab session on VIVADO which have been implemented on Zynq Board (i.e ZedBoard) FPGA, so Student will get complete design skill on VHDL with VIVADO.
You guys can Learn the course while using ISE Design Suit.While VIVADO is successor of ISE so this Course and VHDL Design Methodology is same for ISE based design so do not scare about VIVADO because of it just a latest version of Design tool than ISE.
VHDL (Very High Speed Integrated Circuit Hardware Description Language) is a type of HDL which is developed by IBM, Texas Instrument on the DoD Funding in 70's. TheVHDL has been standardized by IEEE in 1987. Initially VHDL is developed for Configuring Logic Arrays , PLD's while as the invention of FPGA, ASIC this HDL is highly preferred for re-configuring those Logic Gate Arrays.
VHDL has three major section on Programming which is Library, Entity and Architecture. The Library consists of library files as header file on C/C++, the library file define the functions called on the program. The Entity section define all the input and output ports which are going to used on program. And Finally the Architecture Section includes the implementation of any assignment or operation or functionality on VHDL Program.
For this course we have utilized the state of art design tool form Xilinx which is VIVADO while yo can use ISE Design Suit for learning VHDL Programming aside of VIVADO Design suit.
•Data types defines a set of values that a variable can store along with a set of operations that can be performed on the variable.
•So Each variable, port or signal has to be defined on VHDL which is classified as Data Types declaration of variable. Example of Data Types on High Level Programming Language (C Programming Language) are Char, Float, int , double etc.
In VHDL there are different types of data types which can be listed as: bit, Std_logic, integer, real, type etc.
This Lecture covers all the data types of VHDL and how to create user defined data type (also called as Enumerated Data Types) in VHDL.
See the Video and Find the attachment for downloading, installing and Managing 30 day Evaluation license for VIVADO. However this course can be done with ISE Design suit, the interface of VIVADO only the different than ISE.
In this lecture we have designed the NOR Gate on HDL, this Nor gate can be implemented on any Series of FPGA supported by ISE or VIVADO. While we have Zynq Family of FPGA Board which is Zedboard so we have planned the constraint for Zeddboard and we are going to see the output on FPGA on another Session.
This is optional Lecture session actually demonstration of NOR Gate on ZedBoard FPGA. Actually you dont need Zeddboard and VIVADO for learning this course, if you have ISE and other boards that is also good but you have to have idea of constranting those board and the design flow of tool you are using.
In this Session we have simulated the testbench written for NAND gate on VHDL. The VIVADO has powerful simulator intool which is VIVADO Simulator which can be used for Run Behavioural Simulation, Pre/Post synthesis Simulation and Pre/Post Implementation Simulation. We have introduced on this lecture about how to write a testbench on VHDL and how to run that testbench file on VIVADO Simulator for generating simulation Waveform.
Conditional Statement are those statement on VHDL which checks the condition or boolean expression and execute the statement according to the condition. There are different conditional statement on VHDL which are "With Select", "When Else", "Case", "IF Else". This statements has own speciality and syntax which has been talked on the lecture.
In this lecture or Lab 31 we have designed the decoder using when else and case statement. The 2:4 Decoder actually decodes or converts the 2 bit binary data into 4 bit binary format. For implementing 2:4 decoder and simulating it we need to know about the truth table of the logic circuit's.
This lecture is also optional, if you have Zynq device than you can implement your decoder 2:4 in to your board or you can escape the session. In this demo we have presented the providing two inputs form the switch of Zynq Device and getting output on the LED of Board. The Functionality of Decoder has been implemented on the Zynq Board (ZedBoard) in this lab demo.
Combinational Circuit are those circuit which takes some inputs and generated some continational output as logical combination. Example of combinational circuit are Logic Gates, Encoder, Decoder, Multiplexer, De-Multiplexer etc. This logic circuit takes the input checks some specific input state and determine the output on the output ports.
In this lecture we have talked on the combinational circuit basics how to use conditional statement on design of combinational circuit.
Half adder is the type of combinational circuit, in this lab 41 we have designed the Half adder on VHDL in VIVADO Design suit and we proceed the step of implementing the design targeted for Zynq FPGA.
Structural design allow designer/programmer to reuse different modules which are created separately. With this design methodology "One single module can be used number of time, so the code reusability can be achieved. We are going to design Full Adder in this Section (another Lecture) by using Half Adder two times. The Half adder has been designed on the previous lab i.e lab 41.
The Design of Full Adder using Half Adder is the method of Structural Design in VHDL. This structural design methodology is highly used for architect complex projects in to small modules and finally integrating this modules.
For Structural Design there must be careful implementation of two section. In the same project we need to add the previous source (for now half adder) and recent added source module (Full Adder). Full Adder module must include component section which call the entity of Half Adder on Full Adder and after than there must have port mapping section this port mapping interface the Half adder port to the Full Adder Port. If there is no direct connection of half adder ports with full adder ports then there we need signal; signal is a wire or interconnection between one port of module to another module inside of the top module (Full Adder).
Sequential Circuits are those circuits whose values is not just dependent on present input only as in combinational circuit but on past sequence of inputs
In this Lab Session we have imlemented the Binary Coded Decmal (BCD Counter; a 4bit binary counter counts upto 1111 from 0000). This BCD counter utilizes the main clock of FPGA which is 100 MHz in ZedBoard or 50 Mhz of Spartan. That 100 Mhz of Clock has been prescaled (divide) in to 2.667 hz i.e .335 second. Actually 100 MHz of clock generate 10ns of time delay on each led change of BCD counter so the clock prescle to .335 second has been done which is human realiazable delay for led blinking.
The prescaled (divided) clock has been used by Counter Process which counts up the counter from 0000 to 1111. If the counter reach 1111 then the counter will automatically started from 0000.
Finite State Machine is the Problem Solving Approach on Digital Design in which actually the problems has to converted into finite number of state. Each state checks the inputs and provides the output along with there might have some state change happen. FSM Implemented examples are Traffic Light Controller Design, Vending Machine Design, Car Security System Design etc.
We have used this FSM for Sequence Detector Design , actually this FSM implementation checks the input sequence; if the input sequence is 1011 then the detection output will blink else the machine checks the input sequence continuously.
In this Section we have attached the Reference Guide on " VHDL Programming", this reference guide is targeted for intermediate level of learner.
This section is on Basics of Arithmetic and Logical Unit. We have presented the 2 bit ALU , 8 Bit ALU with Register and N bit ALU in this lecture.
This Second section of ALU Design explains about the Register Declaration in VHDL, Generic Implementation and Creating Simulation Testbench for the 8 bit and N bit ALU.
Krishna is an FPGA Engineer and Research Lead at Digitronix Nepal. Krishna had graduated on M.Sc Engineering Degree after B.E in Electronics and Communication Engineering.He has several paper published on IEEE and Google Scholar and he also have requested for Patent for Image Processing IP on FPGA.He is working on FPGA , ASIC and VLSI design and Verification from past 5+ years.He has worked for different multinational companies for FPGA/ASIC/VLSI Design and Verification.There are different IP and Bus verification Digitronix Nepal has marked for Industries.He had worked with different application based projects as Signal Processing for ADAS, IIOT and Computer Vision Applications. He had expertise on FPGA Design with VHDL/Verilog and Tcl with Tools experience of Xilinx ISE, VIVADO and Modelsim. Krishna had worked with Xilinx 7 Series FPGA boards and Ultrascale Boards for different embedded and custom applications.