VHDL Programming with Xilinx ISE & Spartan/Nexys FPGA
0.0 (0 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
5 students enrolled
Wishlisted Wishlist

Please confirm that you want to add VHDL Programming with Xilinx ISE & Spartan/Nexys FPGA to your Wishlist.

Add to Wishlist

VHDL Programming with Xilinx ISE & Spartan/Nexys FPGA

Learn VHDL Programming with Xilinx ISE and Spartan 3E/Nexys FPGA
New
0.0 (0 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
5 students enrolled
Created by Krishna Gaihre
Last updated 9/2017
English
Current price: $10 Original price: $95 Discount: 89% off
5 hours left at this price!
30-Day Money-Back Guarantee
Includes:
  • 3.5 hours on-demand video
  • 1 Article
  • 5 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Learn about VHDL Programming Methodology
  • VHDL Syntax and Semantics
  • Digital Logic Component Design with VHDL
  • Conditional Circuit Design with VHDL
  • Computational and Sequential Circuit Design with VHDL
  • Structural Design with VHDL
  • State Machine Design with VHDL
View Curriculum
Requirements
  • Basic idea of Digital Design
  • Basic Idea of Programming Language
Description

Learn VHDL Programming with Xilinx ISE Design Suit and Spartan/Nexys FPGA.This Course covers from the basics of VHDL Syntax, VHDL Design Methodology, Basic Logic gate design with VHDL, Creating Simulation testbench on ISE , Simulating design, implementing design and testing/verifying functionality on FPGA.

In the third Section Course includes the conditional statement on VHDL, Creating Combinational and Sequential Circuit on VHDL, Structural Design in VHDL and State Machine Design in VHDL. We have Lab Session on each Section so you will be more familiar with labs or doing projects on VHDL with Xilinx ISE Design suit. We also have included the Uploading the Bit file to Spartan/Nexys FPGA and the Demonstration of the Output on the FPGA. 

We also have attached the "VHDL Programming Reference Guide Prepared by Digitronix Nepal" in the course. Meet You in the Course!!!

Who is the target audience?
  • Electrical and Computer Engineering
  • Electronics Engineering
  • Computer Science
Compare to Other VHDL Courses
Curriculum For This Course
15 Lectures
03:36:33
+
Introduction
7 Lectures 01:34:17

•Data types defines a set of values that a variable can store along with a set of operations that can be performed on the variable.

•So Each variable, port or signal has to be defined on VHDL which is classified as Data Types declaration of variable. Example of Data Types on High Level Programming Language (C Programming Language) are Char, Float, int , double etc.

In VHDL there are different types of data types which can be listed as: bit, Std_logic, integer, real, type etc.

This Lecture covers all the data types of VHDL and how to create user defined data type (also called as Enumerated Data Types) in VHDL.

VHDL Data types and Operators
15:39


Section 1 Lab 12 NAND Gate Design and Implementation
26:32

Section 1 Lab 12 Implementation of NAND Gate on FPGA with ISE Impact
01:02


VHDL Reference Guide from Digitronix Nepal: For Beginner to Intermediate Learner
25:17
+
Simulating VHDL Program with Testbench
1 Lecture 19:57

This Section covers the Simulation Methodology on ISE Design Suit with VHDL. simulation is the process of creating virtual environment and manipulating the input variables for getting corresponding output. Creating simullation testbench in VHDL with ISE is simple and we are going to design and simulate NAND gate in this section.

Section 2 Simulation NAND Gate with VHDL and ISE Design Suit
19:57
+
Conditional Statement on VHDL (If else, Case, When Else and With Select)
1 Lecture 19:03

There are different conditional statement on VHDL which can be differentiated as Sequential Statement ( If Else, Case, With Select, When Else) and Concurrent Statement (Process Statement). In this section we have brief overview on this statement and Creating Decoder with this conditional statement.

Section 3 Conditional Statement on VHDL_Design of Decoder
19:03
+
Section 4 Combinational Circuit Design with VHDL
2 Lectures 40:15

Combinational Circuit are those logic circuit which takes input and process it as logical and operation and provides output. This combinational circuit doesnot consists of memory and it might not need to be clock sychrnized.

In this Section we have overview of combinaitonal circuit and types of its, examples of combination of gates, adder, comparator, multiplexer, and decoder.

Section 4_1 Combinational Circuit Design Overview
20:20

Design, Simulation and Implementation of Half Adder in VHDL with ISE Design Suit and Targeted for Spartan 3E and Nexys FPGA.

This is lab session , you will design Half adder in VHDL, create Testbench for simulation, write constraint and synthesize the design, implement the design and generate the programming file.

Section 4_2 Half Adder Design Simulation and Implementation on VHDL with ISE
19:55
+
Section 5 Sequential Circuit Design with VHDL and ISE
1 Lecture 14:32

Sequentual Circuit Design Overview, types of sequential circuit  as Flipflops, Register, counter has been briefed in this lecture. We also have talk on VHDL programming for those sequential circuit's and design methodologies for those circuits with clock triggered methodology.

We have to check Rising Edge of Clock for doing operation on sequential circuit , we have presented two method for checking rising edge on this lecture. 

Section 5 Sequential Circuit Design with VHDL and ISE
14:32
+
Section 6 Structural Design in VHDL: Creating Full Adder using Half Adder
3 Lectures 38:16

Structural Design Overview: how to create different modules on same project, how to integrate them in the top module. The component declaration, Signal declaration and port mapping on Top Module has been explained in this section in detail.

Section 6 Structural Desgin in VHDL with ISE and Spartan_Nexys FPGA
14:53

In this lab you are going to design Half Adder initially and then that Half adder is going to used on Full Adder Module with Structural Design Methodology. For Structural Design Methodology you need to know about Component, Signals and Port Mapping which as been explained in this section clearly.

Join the Course! Happy Learning!

Section 62 Structural Design of Full Adder Design with Half Adder in VHDL/ISE
22:34

Demonstration of Full Adder Implementation on Spartan 3E Starter FPGA Kit. You can check the functionality of full adder on the demo as well as on your FPGA Board.

We will attach the Demo on Nexys 2 Soon.

Section 63 Full_adder_implementation_on_Spartan_3E_FPGA
00:49
About the Instructor
Krishna Gaihre
4.5 Average rating
19 Reviews
172 Students
5 Courses
FPGA Design Engineer with Expertise on Embedded Design

Krishna is an FPGA Engineer and Research Lead at Digitronix Nepal. Krishna had graduated on M.Sc Engineering Degree after B.E in Electronics and Communication Engineering.He has several paper published on IEEE and Google Scholar and he also have requested for Patent for Image Processing IP on FPGA.He is working on FPGA , ASIC and VLSI design and Verification from past 5+ years.He has worked for different multinational companies for FPGA/ASIC/VLSI Design and Verification.There are different IP and Bus verification Digitronix Nepal has marked for Industries.He had worked with different application based projects as Signal Processing for ADAS, IIOT and Computer Vision Applications. He had expertise on FPGA Design with VHDL/Verilog and Tcl with Tools experience of Xilinx ISE, VIVADO and Modelsim. Krishna had worked with Xilinx 7 Series FPGA boards and Ultrascale Boards for different embedded and custom applications.