Learn VHDL Design for use in FPGA and ASIC Digital Systems
3.5 (58 ratings)
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Learn VHDL Design for use in FPGA and ASIC Digital Systems

VHDL Design and Modeling Tutorial for both the beginner and experienced Programmer using a Xilinx FPGA Development Board
3.5 (58 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
1,592 students enrolled
Last updated 11/2016
English
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Includes:
  • 4 hours on-demand video
  • 1 Supplemental Resource
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Describe and explain VHDL syntax and semantics
  • Create synthesizable designs using VHDL
  • Use Xilinx FPGA development board for hand-on experience
  • Design simple and practical test benches in VHDL
  • Use the Xilinx Vivado toolset
  • Design and develop VHDL models
  • Use ModelSim simulation software
View Curriculum
Requirements
  • Familiarity with digital logic design, electrical engineering, or equivalent experience
Description

Teach yourself the analysis and synthesis of digital systems using VHDL to design and simulate FPGA and ASIC digital systems. Participants learn the fundamental concepts of VHDL and practical design techniques using a Xilinx FPGA Development Board and ModelSim simulation software for hands-on experience. The VHDL methodology and design flow for logic synthesis addresses design issues related to component modeling, data flow description in VHDL and behavioral description of hardware. An emphasis is placed on understanding the hardware description language, VHDL design techniques for logic synthesis, design criteria, and VHDL applications.

At the end of this course, participants will be able to accomplish the following:

  • Describe and explain VHDL syntax and semantics
  • Create synthesizable designs using VHDL
  • Use Xilinx FPGA development board for hand-on experience
  • Use the Xilinx ISE toolset
  • Use ModelSim simulation software
  • Design simple and practical test-benches in VHDL
  • Design and develop VHDL models

Prerequisites:

  • Familiarity with digital logic design, electrical engineering, or equivalent experience.

Even if you're now already familiar with VHDL but you've:

  • Never used an attribute other than ‘event?
  • Never used variables?
  • Always used a process where a single concurrent statement would have sufficed?
  • Never used assert or report statements except (maybe) in a test-bench?
  • Never used an unconstrained vector or array?
  • Never used a passive process inside of an entity?
  • Never used a real or the math_real library package in synthesizable code?
  • Always used a single process per signal assignment?

then this course will definitely have something for you as well. You will learn finite state machine design, the two-process design methodology, test-bench design, combinatorial and sequential logic, and extensible synthesizable designs that are reusable.

Who is the target audience?
  • Engineers
  • Hobbyists
  • Makers
  • Engineering Students
  • Engineering Managers
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Curriculum For This Course
Expand All 12 Lectures Collapse All 12 Lectures 03:50:54
+
Basics
2 Lectures 30:50

Read:
Chapter 1 - Fundamental Concepts (pages 1 - 30)
Objectives:
Modeling Digital Systems
Domains and Levels of Modeling
Modeling Languages
VHDL Modeling Concepts
Learning a New Language: Lexical Elements and Syntax

Preview 20:08

Quiz 1
10 questions

Software Tool Installation (no audio)
10:42
+
Data types & operations
2 Lectures 58:29

Read:
Chapter 2 - Scalar Data Types and Operations (pages 31 – 64)
Chapter 4 - Composite Data Types and Operations (pages 95 – 135 / 95 - 136)
Objectives:
Constants and Variables
Scalar Types
Type Classification
Attributes of Scalar Types
Expressions and Operators
Arrays
Unconstrained Array Types
Array Operations and Referencing
Records

Preview 33:28


Quiz 2
10 questions
+
Concurrent statements
1 Lecture 21:21

Read:
Chapter 5 - Basic Modeling Constructs (pages 135 – 200 / 137 - 206)
Objectives:
Entity Declarations and Architecture Bodies
Behavioral Descriptions
Structural Descriptions
Design Processing

Preview 21:21

Quiz 3
10 questions
+
Sequential statements
1 Lecture 23:42

Read:
Chapter 3 - Sequential Statements (pages 65 - 94)
Objectives:
If Statements
Case Statements
Null Statements
Loop Statements
Assertion and Report Statements

Session 4
23:42

Quiz 4
10 questions
+
Processes
1 Lecture 37:11

Read:
Processes
Objectives:
Combinatorial Processes
Sequential Processes
Clocks
Clock Enables
Resets
Two Process Method
State Machines
Sequencers

Session 5
37:11

Quiz 5
10 questions
+
Subprograms
1 Lecture 22:37

Read:
Chapter 6 – Subprograms (pages 201 – 238 / 207 – 244)
Chapter 8 - Resolved Signals (pages 261 - 286)
Objectives:
Procedures
Procedure Parameters
Concurrent Procedure Call Statements
Functions
Overloading
Visibility of Declarations
Basic Resolved Signals
Resolved Signals, Ports, & Parameters

Session 6
22:37

Quiz 6
10 questions
+
Packages
1 Lecture 09:57

Read:
Chapter 7 - Packages and Use Clauses (pages 239 – 260 / 245 – 266)
Chapter 9 – Predefined and Standard Packages (pages 287 – 314 / 293 – 336)
Chapter 12 / 13 - Components and Configurations (pages 335 – 358 / 417 - 448)
Objectives:
Package Declarations
Package Bodies
Use Clauses
The Predefined Packages standard and env
IEEE Standard Packages
Components
Configuring Component Instances
Configuration Specifications

Session 7
09:57

Quiz 7
10 questions
+
Design for synthesis
1 Lecture 09:25

Read:
Chapter 14 / 21 – Design for Synthesis (pages 375 – 411 / 633 – 667)
Objectives:
Synthesizable Subsets
Use of Data Types
Interpretation of Standard Logic Values
Modeling Combinatorial Logic
Modeling Sequential Logic
Modeling Memories
Synthesis Attributes
MetaComments

Session 8
09:25

Quiz 8
10 questions
+
Advanced topics
1 Lecture 13:31

Read:
Chapter 10 / 11 Aliases (pages 315 – 323 / 355 – 363)
Chapter 11 / 12 Generic Constants (pages 325 – 332 / 365 – 372)
Chapter 13 / 14 Generate Statements (pages 359 – 372 / 449 - 473)
Objectives:
Aliases for Data Objects
Aliases for Non-Data Items
Generic Constants
Generate Iterative Structures
Conditionally Generating Structures

Session 9
13:31

Quiz 9
10 questions
+
Additional libraries
1 Lecture 03:51

Read:
Additional libraries

Session 10
03:51

Quiz 10
5 questions
About the Instructor
Clyde R. Visser, P.E.
3.5 Average rating
58 Reviews
1,592 Students
1 Course
Embedded Systems and FPGA Engineer, UCI Extension Instructor

Clyde R. Visser, P.E. is a senior electronics engineer at Physical Optics Corporation. He has a Bachelor of Science degree in Electrical Engineering (BSEE) with emphasis in Computer Engineering received from the California Polytechnic University at Pomona. He has over 30 years engineering experience in the telecommunication, data communication, medical, and power conversion systems industries using embedded systems. He holds one patent, is a licensed electrical engineer, and holds a Technician class amateur radio license. He is also a Senior Member of the Institute of Electrical and Electronic Engineers (IEEE) and is licensed to pratice electrical engineering in the state of California.

Mr. Visser has been designing with FPGAs (Field Programmable Gate Arrays) and PLDs (Programmable Logic Devices) for the majority of his career. He has been designing FPGA logic using VHDL for the past 15 years. He has also taught courses in Embedded Systems Architecture, VHDL Design and Modeling of Digital Systems, and Digital Signal Processing with FPGA's at UC Irvine Extension for the past nine years.