SystemVerilog Design-2: A Professional SoC Code walk-through
4.0 (18 ratings)
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SystemVerilog Design-2: A Professional SoC Code walk-through

VLSI : Learn Verilog / System Verilog for SOC Design - Get exposed to a complete, industry standard project in detail
4.0 (18 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
1,042 students enrolled
Created by Ajith Jose
Last updated 5/2017
English
Current price: $10 Original price: $85 Discount: 88% off
5 hours left at this price!
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Includes:
  • 2.5 hours on-demand video
  • 4 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Write SystemVerilog SoC design code in a professional way
View Curriculum
Requirements
  • This course is a practical session explaining how to a complete SoC design in SystemVerilig and this is not explaining the theory. Thus you need to have the basic knowledge of SystemVerilog Design coding
  • Also you need to have the basic knowledge about Digital Circuits.
Description

SystemVerilog course teaches the concepts of SoC/IC design and it is more of a practical session walk-through. Here, a professional SoC design code is explained in detail. This will enable the student to get exposed to an industry standard SoC code and the techniques behind writing it.

This course is started by explaining the interface feature in SystemVerilog. It explains the usage of interface and few language features like enumeration and macros which are used in the coding example. Next, the process of developing general SV components is explained with examples. Finally, a complete design code of a simple SoC is explained with minute details.

 By taking this course, you will be more confident in writing SV design code as you are learning  the process of developing standard SoC designs. This will be an excellent platform to master design coding styles in SystemVerilog.

Who is the target audience?
  • Students with basic SV design coding knowledge who wants to get exposed to an industry standard SoC design coding project
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Curriculum For This Course
24 Lectures
02:25:45
+
Welcome
1 Lecture 02:22
+
Interface
1 Lecture 08:38
+
Enumeration and Compiler directives
2 Lectures 06:23
Enumeration & User Defined datatype
04:10

Compiler Directives
02:13
+
General Components
5 Lectures 27:56
General Components 1
05:11

General Components 2
03:44

General Macros
04:17

Writing a FIFO
05:17

FIFO Controls
09:27
+
DUT Design Description
3 Lectures 16:19
AXI and OCP Protocol Description
05:20

DUT Description
04:09

AXI-OCP Converter
06:50
+
Code Walk-through : AXI -OCP Conversion
6 Lectures 53:27
AXI Front End Design
03:40

General Components Code
04:15

AXI Write Front End Code
14:26

AXI Read Front End Code
03:10

AXI-OCP Converter - State Machine
14:57

AXI-OCP Converter Code
12:59
+
Code Walk-through : OCP-AXI Conversion
5 Lectures 28:30
OCP Read Return Front End
06:55

OCP-AXI Converter
08:39

Interconnect Code
04:15

Simulation
06:13

Concluding Coding
02:28
+
Summary
1 Lecture 02:10
Summary
02:10
About the Instructor
Ajith Jose
3.9 Average rating
422 Reviews
4,945 Students
7 Courses
Hardware Engineer

A post graduate in electronics engineering with 8+ years of experience in ASIC design & verification using system-verilog with major semiconductor companies like Intel India and ARM UK. A passionate and continuous learner in emerging VLSI methodologies. Enjoys learning new technologies and sharing knowledge.