SystemVerilog course teaches the concepts of SoC/IC design and it is more of a practical session walk-through. Here, a professional SoC design code is explained in detail. This will enable the student to get exposed to an industry standard SoC code and the techniques behind writing it.
This course is started by explaining the interface feature in SystemVerilog. It explains the usage of interface and few language features like enumeration and macros which are used in the coding example. Next, the process of developing general SV components is explained with examples. Finally, a complete design code of a simple SoC is explained with minute details.
By taking this course, you will be more confident in writing SV design code as you are learning the process of developing standard SoC designs. This will be an excellent platform to master design coding styles in SystemVerilog.
A post graduate in electronics engineering with 8+ years of experience in ASIC design & verification using system-verilog with major semiconductor companies like Intel India and ARM UK. A passionate and continuous learner in emerging VLSI methodologies. Enjoys learning new technologies and sharing knowledge.