This course teaches the SystemVerilog language used in the VLSI industry for System-On-Chip design verification. This is primarily focusing on the reusable random testing features of SystemVerilog.
This course contains video lectures of 2 hours duration. It is stared by explaining what is Constraint Random Verification (CRV) and how it can be implemented in a SV TestBench. It explains the concepts of using random variables in a class and how to add different types of constraints to to them. Below summary of the topics covered in this course.
By taking this course, the you will be able to start using CRV support features in SystemVerilog for effective TestBench coding. This course will an excellent platform to grab the magical features of SystemVerilog to build reusable random who understand the basic of it.
A post graduate in electronics engineering with 8+ years of experience in ASIC design & verification using system-verilog with major semiconductor companies like Intel India and ARM UK. A passionate and continuous learner in emerging VLSI methodologies. Enjoys learning new technologies and sharing knowledge.