Find online courses made by experts from around the world.
Take your courses with you and learn anywhere, anytime.
Learn and practice real-world skills and achieve your goals.
The knowledge gained from this course will help you cover those critical and hard to find design bugs. SystemVerilog Functional Coverage Language and Methodology is a very important part of overall functional verification methodology and all verification engineers need this knowledge to be successful. The knowledge of FC will indeed be a highlight of your resume when seeking a challenging job or project The course offers step-by-step guide to learning of FC with real life applications to help you solidify your concepts and apply FC to your project in shortest possible time. FC helps the critical part of Functional/Temporal domain coverage which is simply not possible with code coverage.The course does not require any prior knowledge of SystemVerilog or OOP (Object oriented programming) or UVM. The course has 9 lectures that will take you step by step through FC language from scratch.
Not for you? No problem.
30 day money back guarantee.
Learn on the go.
Desktop, iOS and Android.
Certificate of completion.
|Section 1: Introduction and Methodology|
This lecture will establish the role of Functional Coverage under the IEEE-1800 SystemVerilog umbrella. It will also highlight the difference between code coverage and functional coverage.
This lecture will show you the Functional Coverage Methodology which encompasses, SystemVerilog Assertions (SVA) 'cover' + SystemVerilog Functional Coverage + Code Coverage. It also shows you how you can automate Test => Simulation => Coverage Evaluation => Test enhancement loop to reach a 100% coverage goal.
|Section 2: SystemVerilog Functional Coverage Language Features|
in-depth discussion on syntax/semantics and applications of SystemVerilog 'covergroup' and 'coverpoint'
in-depth discussion on syntax/semantics and applications of SystemVerilog 'coverpoint' 'bins'
in-depth discussion on syntax/semantics and applications of SystemVerilog 'cross' coverage
in-depth discussion on syntax/semantics and applications of SystemVerilog 'transition' coverage.
in-depth discussion on syntax/semantics and applications of various bin types.
|Section 3: Performance implications and coverage methodology|
|In this lecture, you will learn about 'what you should cover', 'when you should cover', and the performance implications thereof.|
In this lecture, you will learn about Coverage options such as 'weight' 'auto_bin_max' etc. instance specific options. Examples will solidify the usage of these options
Ashok Mehta has worked in the CPU/SoC design and verification field for over 30 years at DEC, INTEL, APPLIED MICRO (AMCC) and TSMC.
Ashok is author of the popular book “SystemVerilog Assertions and Functional Coverage: A guide to language, methodology and applications”. Springer-2014
Ashok holds 13 U.S. Patents in the field of SoC and 3DIC design verification.