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SystemVerilog Functional Coverage Language/methodology/apps

Step-by-step overview of SystemVerilog Functional Coverage features, syntax/semantics, methodology/apps FROM SCRATCH
4.3 (91 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
3,000 students enrolled
Created by Ashok Mehta
Last updated 3/2016
  • 1.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
Get you up and running in the shortest possible time. No knowledge of SystemVerilog OOP or UVM required
Make you confident in seeing that you have fully 'functionally' covered your design and testbench before tape-out
Make you knowledgeable in one of the most important and critical part of overall Design Verification landscape
Will make your resume even stronger in the competitive DV landscape.
View Curriculum
  • This course will go step-by-step through each of Functional Coverage (FC) language feature and methodology component with practical applications at each step - FROM SCRATCH
  • You only need very basic knowledge of hardware design and verification
  • You do NOT need knowledge of Object Oriented Programming (OOP) or Universal Verification Methodology (UVM)

The knowledge gained from this course will help you cover those critical and hard to find design bugs. SystemVerilog Functional Coverage Language and Methodology is a very important part of overall functional verification methodology and all verification engineers need this knowledge to be successful. The knowledge of FC will indeed be a highlight of your resume when seeking a challenging job or project The course offers step-by-step guide to learning of FC with real life applications to help you solidify your concepts and apply FC to your project in shortest possible time. FC helps the critical part of Functional/Temporal domain coverage which is simply not possible with code coverage.The course does not require any prior knowledge of SystemVerilog or OOP (Object oriented programming) or UVM. The course has 9 lectures that will take you step by step through FC language from scratch.

Who is the target audience?
  • Hardware design and verification engineers, Verification IP developers and EDA application engineers are best suited for this course.
  • New college graduates will also benefit tremendously from this course.
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Curriculum For This Course
Expand All 9 Lectures Collapse All 9 Lectures 01:39:03
Introduction and Methodology
2 Lectures 21:37

This lecture will establish the role of Functional Coverage under the IEEE-1800 SystemVerilog umbrella. It will also highlight the difference between code coverage and functional coverage.


This lecture will show you the Functional Coverage Methodology which encompasses, SystemVerilog Assertions (SVA) 'cover' + SystemVerilog Functional Coverage + Code Coverage. It also shows you how you can automate Test => Simulation => Coverage Evaluation => Test enhancement loop to reach a 100% coverage goal.

Functional Coverage: Methodology
SystemVerilog Functional Coverage Language Features
5 Lectures 01:02:20

in-depth discussion on syntax/semantics and applications of SystemVerilog 'covergroup' and 'coverpoint'

covergroup and coverpoint

in-depth discussion on syntax/semantics and applications of SystemVerilog 'coverpoint' 'bins'

coverpoint 'bins'

in-depth discussion on syntax/semantics and applications of SystemVerilog 'cross' coverage

'cross' coverage

in-depth discussion on syntax/semantics and applications of SystemVerilog 'transition' coverage.

'transition' coverage

in-depth discussion on syntax/semantics and applications of various bin types.

widlcard bins, illegal_bins, ignore_bins, binsof, intersect
Performance implications and coverage methodology
2 Lectures 15:06
In this lecture, you will learn about 'what you should cover', 'when you should cover', and the performance implications thereof.
Performance implications and coverage methodology

In this lecture, you will learn about Coverage options such as 'weight' 'auto_bin_max' etc. instance specific options. Examples will solidify the usage of these options

coverage options and examples
About the Instructor
4.3 Average rating
121 Reviews
3,064 Students
2 Courses
30 years as SoC designer. Author: SVA+FC book.13 US Patents.

Ashok Mehta has worked in the CPU/SoC design and verification field for over 30 years at DEC, INTEL, APPLIED MICRO (AMCC) and TSMC.

Ashok is author of the popular book “SystemVerilog Assertions and Functional Coverage: A guide to language, methodology and applications”. Springer-2014

Ashok holds 13 U.S. Patents in the field of SoC and 3DIC design verification.

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