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SystemVerilog Assertions and Functional Coverage is a comprehensive from-scratch course on Assertions and Functional Coverage that covers features of SV LRM 2005/2009 and 2012. The course does not require any prior knowledge of OOP or UVM. The course is taught by a 30 year veteran in the design of CPU and SoC who published a book on SVA and FC in 2014 and hold 13 U.S. patents on design verification. The course has 33 lectures and is 8.5 hours in length that will take you step by step through learning of the languages.
The knowledge gained from this course will help you find and cover those critical and hard to find and cover design bugs. SystemVerilog Assertions and Functional Coverage are very important parts of overall functional verification methodology and all verification engineers need this knowledge to be successful. The knowledge of SVA and FC will indeed be highlights of your resume when seeking a challenging job or project The course offers step-by-step guide to learning of SVA and FC with plenty of real life applications to help you apply SVA and FC to your project in shortest possible time. SVA and FC helps critical aspect of Functional/Temporal domain coverage which is simply not possible with code coverage.
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|Section 1: Welcome and introduction to SystemVerilog Assertions|
|This lecture will provide an introduction to SystemVerilog Assertions, its evolution from PSL, Sugar, etc. and clearly outline course objectives|
We will discuss the basic definition of an Assertion. Its pros and cons and project wide methodology
|Section 2: Immediate Assertions|
This lecture will introduce Immediate Assertions and Deferred Immediate Assertions
|Section 3: Concurrent Assertions – Basics|
This lecture will discuss in-depth the definitions of sequence, property, assert and cover. It will also discuss Implication Operators such as Overlapping and Non-overlapping. This lecture is foundational to the course.
This lecture will discuss how SystemVerilog Assertions are sampled in the pre-poned region of a clock edge. It will discuss nuances of singly clocked properties.
This lecture discusses the most fundamental semantic of the language - that being the concept of multi-threading and pipelined behavior. It then goes into the discussion of formal and actual arguments and their connectivity. other features discussed are assertion execution terminate system features such as 'disable iff'
SVA allows you to write properties / assertions for either VHDL or Verilog design. You write the assertions in SVA and 'bind' those to either VHDL or Verilog RTL.
|Section 4: Concurrent Assertions – Sampled Value Function|
This lecture discusses the so-called Sampled Value Functions, namely $rose and $fell
This lecture discusses Sampled Value Functions such as $past, $stable, $changed, $sampled, etc. It also discusses Global clocking PAST and FUTURE sampled value functions.
|Section 5: Concurrent Assertions – Operators|
This lecture discusses fundamentals of Clock Delay and Clock Delay Range operators.
This lecture dives deep into the Consecutive Repetition Operator.
This lecture dives deep into Non-Consecutive repetition and Non-Consecutive GOTO operators. Shows the similarity and differences between the two operators
This lecture discusses the operators "throughout' and 'within'
This lecture discusses the operators 'and', 'or' and 'intersect' as applied to procedural code as well as concurrent assertion.
This lecture discusses the important concept of 'first_match' and its effective use in an Antecedent. It then follows with if-then-else, iff and 'implies' features
|Section 6: System Functions and Tasks|
$onehot, $onehot0, $isunknown, $countones
Assertion execution control tasks: $assertoff, $asserton, $assertkill, $assertpassoff, $assertpasson, $assertfailoff, $assertfailon, $assertnonvacuouson, $assertvacuousoff, $assertcontrol
|Section 7: Multiply clocked properties and sequences|
|16.Multiply clocked sequences. Multiply clocked properties: ‘and’, ‘or’, ‘not’ operators. Multiple Clock resolution|
|Section 8: Local Variables and Endpoint sequence methods|
This lectures dives deep into SystemVerilog Assertions (SVA) 'Local Variables'. Plenty of applications are given.
.triggered, .matched, Calling subroutines, sequence as a formal argument, sequen
|Section 9: Misc IMPORTANT Topics|
This lecture discusses 'expect', 'assume', Blocking 'action block' etc. important features of SVA.
This lecture shows how to write SVA assertion for an Asynchronous FIFO.
|Section 10: IEEE-1800: LRM 2009/2012 features|
This lecture discusses the IEEE-1800 LRM 2009 and 2012 features such as 'let declarations' and 'checker'
|Section 11: QUIZ 1: Synchronous FIFO QUIZ 2: Up-Down Counter|
This is actually Quiz #1. A synchronous FIFO design is presented and questions are posed for which you have to write assertions.
|This is actually Quiz #2. An up-down counter design is presented and questions are posed for which you have to write assertions.|
|Section 12: SystemVerilog Functional Coverage Introduction and Methodology|
|This lecture will establish the role of Functional Coverage under the IEEE-1800 SystemVerilog umbrella. It will also highlight the difference between code coverage and functional coverage.|
|This lecture will show you the Functional Coverage Methodology which encompasses, SystemVerilog Assertions (SVA) 'cover' + SystemVerilog Functional Coverage + Code Coverage. It also shows you how you can automate Test => Simulation => Coverage Evaluation => Test enhancement loop to reach a 100% coverage goal.|
|Section 13: SystemVerilog Functional Coverage Language Features|
|in-depth discussion on syntax/semantics and applications of SystemVerilog 'covergroup' and 'coverpoint'|
|in-depth discussion on syntax/semantics and applications of SystemVerilog 'coverpoint' 'bins'|
|in-depth discussion on syntax/semantics and applications of SystemVerilog 'cross' coverage|
|in-depth discussion on syntax/semantics and applications of SystemVerilog 'transition' coverage.|
|in-depth discussion on syntax/semantics and applications of various bin types.|
|Section 14: Performance implications and coverage methodology|
In this lecture, you will learn about 'what you should cover', 'when you should cover', and the performance implications thereof.
|In this lecture, you will learn about Coverage options such as 'weight' 'auto_bin_max' etc. instance specific options. Examples will solidify the usage of these options|
Ashok Mehta has worked in the CPU/SoC design and verification field for over 30 years at DEC, INTEL, APPLIED MICRO (AMCC) and TSMC.
Ashok is author of the popular book “SystemVerilog Assertions and Functional Coverage: A guide to language, methodology and applications”. Springer-2014
Ashok holds 13 U.S. Patents in the field of SoC and 3DIC design verification.