SOC Verification using SystemVerilog

A comprehensive course that teaches System on Chip design verification concepts and coding in SystemVerilog Language
  • Lectures 35
  • Video 5 Hours
  • Skill level all level
  • Languages English
  • Includes Lifetime access
    30 day money back guarantee!
    Available on iOS and Android
    Certificate of Completion

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Course Description

This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language - which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.

Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course

What are the requirements?

  • Basic digital design or awareness to chip design flows
  • Passion for learning

What am I going to get from this course?

  • Over 35 lectures and 4.5 hours of content!
  • Learn the important concepts in SOC/ASIC/VLSI design verification flow
  • Learn the System Verilog language for Functional Verification usage
  • Be ready and qualified for a Verification job in semiconductor industry
  • Udemy Certification on successful course completion
  • Be able to code, simulate and verify SystemVerilog Testbenches

What is the target audience?

  • Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry
  • Digital Design and Verification Professionals who are passionate about continuous learning

What you get with this course?

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30 day money back guarantee

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Lifetime access

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Certificate of completion

Curriculum

Section 1: Welcome to Course - Introduction
04:15

Brief introduction and overview of course - course goals, expectations, teaching methods etc.

05:00

Introduces what is an SOC and what is a SOC/VLSI design flow is

Course Resources
1 slide
Testing Awareness before we start
4 questions
Section 2: Verification Concepts Explained
07:23

Basic concepts of what is verification, why it is done and how it is done

09:17

Explains concepts of verification plan, approaches, levels of verification and verification metrics

13:57

This lecture explains simulation based verification, Formal and Semi-Formal Verification and Assertion based Verification

12:59

Explains and compares Directed vs Random Testing and Coverage Metrics and usage

08:14

Explains latest trends like Accelerated Simulation, Emulation and a wrap up Summary on this Section

Test your Verification Concepts now
5 questions
Section 3: Introduction to System Verilog Language
06:20

Introduction to System Verilog language - History and evolution

10:41

Basic design/TB structure and details on data types and operators in SV language explained

06:59

Loops and Control flow related constructs explained - if/else, for/repeat/while, case/casex/z etc

05:06

Explains System Verilog language support for subroutines - Tasks and Functions

13:53

Explains SV support for Arrays (Fixed/Dynamic/Associative) and Queues

Test Your System Verilog Language Basics now
5 questions
Section 4: Basic SV TB - Connecting to your design
08:40

Explains the interface construct used for abstracting connectivity information between modules

05:26

Clocking blocks construct used for specifying timing information explained with examples

06:16

Explains System Verilog Program Block Constructs

4 slides

System Verilog DPI explained. This alone is a presentation file with no video as of now. A video based lecture will be presented shortly

Test - How much more you know now !
4 questions
Section 5: SV - OOP concepts and Randomization
07:34

General basic OOP concepts explains - inheritance, composition, polymorphism

15:01

Explains Class definitions, Inheritance, polymorphism usage, const, static and abstract classes

07:35

Explains Virtual Interfaces and how it is used for connecting dynamic world of classes to static world of modules

09:42

Basics of creating random constraints in System verilog explained - simple randomness, simple constraints, implicaiton constraint, loop/array constraint etc

08:00

Continuation of Random constraints - explains distribution constraints, layered constraints and a full example of how it is all used together

Test - What have you learned more now ?
5 questions
Section 6: Threads and Inter Process Communication
06:22

Explains the concepts of processes and threads in System Verilog and how to implement those

06:50

Explains the concepts of System Verilog Mailboxes and its usages

08:45

Explains System Verilog Events and Semaphores implementation and usage in inter process handshake and synchronization

Test your knowledge now on Advanced System Verilog
4 questions
Section 7: Project Assignment - Building a Testbench for Ethernet Switch
09:08

A case study of applying all verification concepts learned so far to a real design verification problem

5 slides

Here is an exercise for you to code a simple design using language constructs. We will use the same design in our future exercises to build a testbench around and to verify the same. Please discuss your solutions in comments section with the student community

2 slides

In this exercise - create an interface for same design as in Exercise2 along with mod ports for monitor and driver and clocking blocks

7 slides

This is an exercise to start coding basic testbench components. Follow instructions. I will also convert this to a video lecture shortly

7 slides

Exercise to build remaining Test bench components and to extend previous components by implementing mailboxes

6 slides

Last exercise to build the top level testbench and instantiate all components

Section 8: Introduction to Verification Methodologies
08:17

Explains the need and history of Industry standard verification methodologies

06:15

Brief introduction to OVM/UVM methodologies and their highlights

Section 9: Course Wrapup and Summary
04:50

Course wrap up summary and possible future course topics.Feel free to comment on the content or improvements required.

Also visit my new verification excellence school to learn about SVA and coverage and other upcoming courses

http://verificationexcellence.usefedora.com/

thanks

Ramdas

Text

A short survey that helps me get feedback on what improvements can be made

Final Test - Are you ready for a Verification Job now?
2 questions

Instructor Biography

Ramdas Mozhikunnath M , Expert Verification Engineer

Expert and Passionate Verification Engineer having several years of experience in design verification of complex Microprocessors, ASIC and SOC designs at major semiconductor companies like Intel, IBM and other exciting startups. Passionate in continuous learning of new and interesting technologies and always ready to share knowledge and help others

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Reviews

Average Rating
4.4
Details
  1. 5 Stars
    25
  2. 4 Stars
    18
  3. 3 Stars
    3
  4. 2 Stars
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  5. 1 Stars
    0
    • Bhagyalaxmi Parmar

    Very good and interesting course

    I thoroughly enjoyed this course and hence gained enough and needed knowledge out of these sessions. i am grateful to the author

    • Patel Vaishaliben Dilipkumar

    Does the production quality meet your expectations?

    Yes. Good material depicted and good exercise and quiz given.

    • Subash babu

    Good

    I think some more examples with real time use in design. It will very good and easy to learn.

    • Gaurav Kumar Yadav

    Happy with the content

    Feeling satisfied

    • Prudvi Raj

    Basics of system verilog

    very good course to start learning system verilog

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