SOC Verification using SystemVerilog

A comprehensive course that teaches System on Chip design verification concepts and coding in SystemVerilog Language
  • Lectures 35
  • Video 5 Hours
  • Skill level all level
  • Languages English
  • Includes Lifetime access
    30 day money back guarantee!
    Available on iOS and Android
    Certificate of Completion

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Course Description

This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language - which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.

Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course

What are the requirements?

  • Basic digital design or awareness to chip design flows
  • Passion for learning

What am I going to get from this course?

  • Over 35 lectures and 4.5 hours of content!
  • Learn the important concepts in SOC/ASIC/VLSI design verification flow
  • Learn the System Verilog language for Functional Verification usage
  • Be ready and qualified for a Verification job in semiconductor industry
  • Udemy Certification on successful course completion
  • Be able to code, simulate and verify SystemVerilog Testbenches

What is the target audience?

  • Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry
  • Digital Design and Verification Professionals who are passionate about continuous learning

What you get with this course?

Not for you? No problem.
30 day money back guarantee

Forever yours.
Lifetime access

Learn on the go.
Desktop, iOS and Android

Get rewarded.
Certificate of completion


Section 1: Welcome to Course - Introduction

Brief introduction and overview of course - course goals, expectations, teaching methods etc.


Introduces what is an SOC and what is a SOC/VLSI design flow is

Course Resources
1 幻灯片
Testing Awareness before we start
4 个问题
Section 2: Verification Concepts Explained

Basic concepts of what is verification, why it is done and how it is done


Explains concepts of verification plan, approaches, levels of verification and verification metrics


This lecture explains simulation based verification, Formal and Semi-Formal Verification and Assertion based Verification


Explains and compares Directed vs Random Testing and Coverage Metrics and usage


Explains latest trends like Accelerated Simulation, Emulation and a wrap up Summary on this Section

Test your Verification Concepts now
5 个问题
Section 3: Introduction to System Verilog Language

Introduction to System Verilog language - History and evolution


Basic design/TB structure and details on data types and operators in SV language explained


Loops and Control flow related constructs explained - if/else, for/repeat/while, case/casex/z etc


Explains System Verilog language support for subroutines - Tasks and Functions


Explains SV support for Arrays (Fixed/Dynamic/Associative) and Queues

Test Your System Verilog Language Basics now
5 个问题
Section 4: Basic SV TB - Connecting to your design

Explains the interface construct used for abstracting connectivity information between modules


Clocking blocks construct used for specifying timing information explained with examples


Explains System Verilog Program Block Constructs

4 幻灯片

System Verilog DPI explained. This alone is a presentation file with no video as of now. A video based lecture will be presented shortly

Test - How much more you know now !
4 个问题
Section 5: SV - OOP concepts and Randomization

General basic OOP concepts explains - inheritance, composition, polymorphism


Explains Class definitions, Inheritance, polymorphism usage, const, static and abstract classes


Explains Virtual Interfaces and how it is used for connecting dynamic world of classes to static world of modules


Basics of creating random constraints in System verilog explained - simple randomness, simple constraints, implicaiton constraint, loop/array constraint etc


Continuation of Random constraints - explains distribution constraints, layered constraints and a full example of how it is all used together

Test - What have you learned more now ?
5 个问题
Section 6: Threads and Inter Process Communication

Explains the concepts of processes and threads in System Verilog and how to implement those


Explains the concepts of System Verilog Mailboxes and its usages


Explains System Verilog Events and Semaphores implementation and usage in inter process handshake and synchronization

Test your knowledge now on Advanced System Verilog
4 个问题
Section 7: Project Assignment - Building a Testbench for Ethernet Switch

A case study of applying all verification concepts learned so far to a real design verification problem

5 幻灯片

Here is an exercise for you to code a simple design using language constructs. We will use the same design in our future exercises to build a testbench around and to verify the same. Please discuss your solutions in comments section with the student community

2 幻灯片

In this exercise - create an interface for same design as in Exercise2 along with mod ports for monitor and driver and clocking blocks

7 幻灯片

This is an exercise to start coding basic testbench components. Follow instructions. I will also convert this to a video lecture shortly

7 幻灯片

Exercise to build remaining Test bench components and to extend previous components by implementing mailboxes

6 幻灯片

Last exercise to build the top level testbench and instantiate all components

Section 8: Introduction to Verification Methodologies

Explains the need and history of Industry standard verification methodologies


Brief introduction to OVM/UVM methodologies and their highlights

Section 9: Course Wrapup and Summary

Course wrap up summary and possible future course topics.Feel free to comment on the content or improvements required.

Also visit my new verification excellence school to learn about SVA and coverage and other upcoming courses




A short survey that helps me get feedback on what improvements can be made

Final Test - Are you ready for a Verification Job now?
2 个问题

Instructor Biography

Ramdas Mozhikunnath M , Expert Verification Engineer

Expert and Passionate Verification Engineer having several years of experience in design verification of complex Microprocessors, ASIC and SOC designs at major semiconductor companies like Intel, IBM and other exciting startups. Passionate in continuous learning of new and interesting technologies and always ready to share knowledge and help others

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Average Rating
  1. 5 Stars
  2. 4 Stars
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  5. 1 Stars
    • Subash babu


    I think some more examples with real time use in design. It will very good and easy to learn.

    • Gaurav Kumar Yadav

    Happy with the content

    Feeling satisfied

    • Prudvi Raj

    Basics of system verilog

    very good course to start learning system verilog

    • Yukti Shukla

    not satisfied

    If you are explaining something new to students then giving only an outer block with just comments is not should give a proper full code for the exercise for packet generator, driver, Test, Monitor, Scoreboard, Top module, for proper understanding, atleast for one exercise for reference and then you can give several exercises for students to practice. Thanks Yukti

    • Roshni Uppala

    Good start to System Verilog - Great concise course

    I really enjoyed taking this class. It is concise and very easy to follow. The instructor has definitely spent quality time in making this presentations effective. It gives you a good knowledge of testbenches, coding with system verilog. If you have basic verilog experience this a great place to start learning system verilog. I hope pdf's and more detailed explanation to the assignments would be provide shortly. The discussion forums are quick and you will pretty much get your reply soon. Enjoy !

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