Expert and Passionate Verification Engineer having several years of experience in design verification of complex Microprocessors, ASIC and SOC designs at major semiconductor companies like Intel, IBM and other exciting startups. Passionate in continuous learning of new and interesting technologies and always ready to share knowledge and help others
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This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language - which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.
Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course
Brief introduction and overview of course - course goals, expectations, teaching methods etc.
Introduces what is an SOC and what is a SOC/VLSI design flow is
Basic concepts of what is verification, why it is done and how it is done
Explains concepts of verification plan, approaches, levels of verification and verification metrics
This lecture explains simulation based verification, Formal and Semi-Formal Verification and Assertion based Verification
Explains and compares Directed vs Random Testing and Coverage Metrics and usage
Explains latest trends like Accelerated Simulation, Emulation and a wrap up Summary on this Section
Introduction to System Verilog language - History and evolution
Basic design/TB structure and details on data types and operators in SV language explained
Loops and Control flow related constructs explained - if/else, for/repeat/while, case/casex/z etc
Explains System Verilog language support for subroutines - Tasks and Functions
Explains SV support for Arrays (Fixed/Dynamic/Associative) and Queues
Explains the interface construct used for abstracting connectivity information between modules
Clocking blocks construct used for specifying timing information explained with examples
Explains System Verilog Program Block Constructs
System Verilog DPI explained. This alone is a presentation file with no video as of now. A video based lecture will be presented shortly
General basic OOP concepts explains - inheritance, composition, polymorphism
Explains Class definitions, Inheritance, polymorphism usage, const, static and abstract classes
Explains Virtual Interfaces and how it is used for connecting dynamic world of classes to static world of modules
Basics of creating random constraints in System verilog explained - simple randomness, simple constraints, implicaiton constraint, loop/array constraint etc
Continuation of Random constraints - explains distribution constraints, layered constraints and a full example of how it is all used together
Explains the concepts of processes and threads in System Verilog and how to implement those
Explains the concepts of System Verilog Mailboxes and its usages
Explains System Verilog Events and Semaphores implementation and usage in inter process handshake and synchronization
A case study of applying all verification concepts learned so far to a real design verification problem
Here is an exercise for you to code a simple design using language constructs. We will use the same design in our future exercises to build a testbench around and to verify the same. Please discuss your solutions in comments section with the student community
In this exercise - create an interface for same design as in Exercise2 along with mod ports for monitor and driver and clocking blocks
This is an exercise to start coding basic testbench components. Follow instructions. I will also convert this to a video lecture shortly
Exercise to build remaining Test bench components and to extend previous components by implementing mailboxes
Last exercise to build the top level testbench and instantiate all components
Explains the need and history of Industry standard verification methodologies
Brief introduction to OVM/UVM methodologies and their highlights
Course wrap up summary and possible future course topics.Feel free to comment on the content or improvements required.
Also visit my new verification excellence school to learn about SVA and coverage and other upcoming courses
A short survey that helps me get feedback on what improvements can be made
I really enjoyed taking this class. It is concise and very easy to follow. The instructor has definitely spent quality time in making this presentations effective. It gives you a good knowledge of testbenches, coding with system verilog. If you have basic verilog experience this a great place to start learning system verilog. I hope pdf's and more detailed explanation to the assignments would be provide shortly. The discussion forums are quick and you will pretty much get your reply soon. Enjoy !
This course is an excellent introduction to Verification in general and also the SystemVerilog Language used for Verification. As a design engineer I learnt more about Verification and would be incorporating these concepts in my future projects. It is highly recommended to do the exercise given as it will clear many of your doubts. Mr. Ramdas has truly done a commendable job, which is not available in any other online Course Catalogs.
covers all concepts
Quality material with good explanation and exercises