SOC Verification using SystemVerilog

A comprehensive course that teaches System on Chip design verification concepts and coding in SystemVerilog Language
17 reviews
TAUGHT BY
  • Ramdas M Expert Verification Engineer

    Expert and Passionate Verification Engineer having several years of experience in design verification of complex Microprocessors, ASIC and SOC designs at major semiconductor companies like Intel, IBM and other exciting startups. Passionate in continuous learning of new and interesting technologies and always ready to share knowledge and help others

WHAT'S INSIDE
  • Lifetime access to 35 lectures and 7 quizzes
  • 4+ hours of high quality content
  • A community of 5500+ students learning together!
  • 120+ discussions
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SOC Verification using SystemVerilog

A comprehensive course that teaches System on Chip design verification concepts and coding in SystemVerilog Language
17 reviews

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COURSE DESCRIPTION

This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language - which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.

Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course

    • Basic digital design or awareness to chip design flows
    • Passion for learning
    • Over 35 lectures and 4.5 hours of content!
    • Learn the important concepts in SOC/ASIC/VLSI design verification flow
    • Learn the System Verilog language for Functional Verification usage
    • Be ready and qualified for a Verification job in semiconductor industry
    • Udemy Certification on successful course completion
    • Be able to code, simulate and verify SystemVerilog Testbenches
    • Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry
    • Digital Design and Verification Professionals who are passionate about continuous learning

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CURRICULUM

  • SECTION 1:
    Welcome to Course - Introduction
  • 1
    Introduction and Overview
    04:15

    Brief introduction and overview of course - course goals, expectations, teaching methods etc.

  • 2
    Introduction to SOC and VLSI design flows
    05:00

    Introduces what is an SOC and what is a SOC/VLSI design flow is

  • 3
    Course Resources
    1 slide
  • 4
    Testing Awareness before we start
    4 questions
  • SECTION 2:
    Verification Concepts Explained
  • 5
    Verification - What, Why and How ?
    07:23

    Basic concepts of what is verification, why it is done and how it is done

  • 6
    Verification - Planning, Approaches, Metrics
    09:17

    Explains concepts of verification plan, approaches, levels of verification and verification metrics

  • 7
    Verification Methodologies - Simulation, Formal, Assertions
    13:57

    This lecture explains simulation based verification, Formal and Semi-Formal Verification and Assertion based Verification

  • 8
    Directed vs Constrained Random Verification - Coverage
    12:59

    Explains and compares Directed vs Random Testing and Coverage Metrics and usage

  • 9
    Other Trends - HW+SW Verification, Emulation
    08:14

    Explains latest trends like Accelerated Simulation, Emulation and a wrap up Summary on this Section

  • 10
    Test your Verification Concepts now
    5 questions
  • SECTION 3:
    Introduction to System Verilog Language
  • 11
    History and Language usage overview
    06:20

    Introduction to System Verilog language - History and evolution

  • 12
    Language Constructs - Data types and Operators
    10:41

    Basic design/TB structure and details on data types and operators in SV language explained

  • 13
    Language Constructs - Loops and Control Flows
    06:59

    Loops and Control flow related constructs explained - if/else, for/repeat/while, case/casex/z etc

  • 14
    Tasks and Functions
    05:06

    Explains System Verilog language support for subroutines - Tasks and Functions

  • 15
    Arrays and Queues
    13:53

    Explains SV support for Arrays (Fixed/Dynamic/Associative) and Queues

  • 16
    Test Your System Verilog Language Basics now
    5 questions
  • SECTION 4:
    Basic SV TB - Connecting to your design
  • 17
    Interfaces
    08:40

    Explains the interface construct used for abstracting connectivity information between modules

  • 18
    Clocking Blocks
    05:26

    Clocking blocks construct used for specifying timing information explained with examples

  • 19
    Program Blocks
    06:16

    Explains System Verilog Program Block Constructs

  • 20
    Direct Programming Interface (DPI)
    4 slides

    System Verilog DPI explained. This alone is a presentation file with no video as of now. A video based lecture will be presented shortly

  • 21
    Test - How much more you know now !
    4 questions
  • SECTION 5:
    SV - OOP concepts and Randomization
  • 22
    Basic OOP Concepts
    07:34

    General basic OOP concepts explains - inheritance, composition, polymorphism

  • 23
    System Verilog Classes Explained
    15:01

    Explains Class definitions, Inheritance, polymorphism usage, const, static and abstract classes

  • 24
    Virtual Interfaces
    07:35

    Explains Virtual Interfaces and how it is used for connecting dynamic world of classes to static world of modules

  • 25
    Random Constraints and usages - Part 1
    09:42

    Basics of creating random constraints in System verilog explained - simple randomness, simple constraints, implicaiton constraint, loop/array constraint etc

  • 26
    Random Constraints - Part 2
    08:00

    Continuation of Random constraints - explains distribution constraints, layered constraints and a full example of how it is all used together

  • 27
    Test - What have you learned more now ?
    5 questions
  • SECTION 6:
    Threads and Inter Process Communication
  • 28
    Processes and Threads in System Verilog
    06:22

    Explains the concepts of processes and threads in System Verilog and how to implement those

  • 29
    System Verilog Mailboxes
    06:50

    Explains the concepts of System Verilog Mailboxes and its usages

  • 30
    Synchronization - Events and Semaphores
    08:45

    Explains System Verilog Events and Semaphores implementation and usage in inter process handshake and synchronization

  • 31
    Test your knowledge now on Advanced System Verilog
    4 questions
  • SECTION 7:
    Project Assignment - Building a Testbench for Ethernet Switch
  • 32
    Exercise 1: Case Study on a Design to be verified
    09:08

    A case study of applying all verification concepts learned so far to a real design verification problem

  • 33
    Exercise 2: Coding exercise to build a Design to be Verified OR Review example
    5 slides

    Here is an exercise for you to code a simple design using language constructs. We will use the same design in our future exercises to build a testbench around and to verify the same. Please discuss your solutions in comments section with the student community

  • 34
    Exercise 3: Coding Interfaces and Clocking Blocks to connect
    2 slides

    In this exercise - create an interface for same design as in Exercise2 along with mod ports for monitor and driver and clocking blocks

  • 35
    Exercise 4: Building Class based Testbench components
    7 slides

    This is an exercise to start coding basic testbench components. Follow instructions. I will also convert this to a video lecture shortly

  • 36
    Exercise 5: Connecting all TB components using mailboxes
    7 slides

    Exercise to build remaining Test bench components and to extend previous components by implementing mailboxes

  • 37
    Exercise 6: Build the top TB with DUT, compile and simulate
    6 slides

    Last exercise to build the top level testbench and instantiate all components

  • SECTION 8:
    Introduction to Verification Methodologies
  • 38
    Standard Verification Methodologies - Need and evolution
    08:17

    Explains the need and history of Industry standard verification methodologies

  • 39
    Introduction to concept of OVM and UVM
    06:15

    Brief introduction to OVM/UVM methodologies and their highlights

  • SECTION 9:
    Course Wrapup and Summary
  • 40
    Summary and learnings and future topics
    04:50

    Course wrap up summary and possible future course topics.Feel free to comment on the content or improvements required.

    Also visit my new verification excellence school to learn about SVA and coverage and other upcoming courses

    http://verificationexcellence.usefedora.com/

    thanks

    Ramdas

  • 41
    Course Improvement Survey
    Text

    A short survey that helps me get feedback on what improvements can be made

  • 42
    Final Test - Are you ready for a Verification Job now?
    2 questions

UDEMY BY THE NUMBERS

5,200,000
Hours of video content
19,000,000
Course Enrollments
5,800,000
Students

RATING

  • 12
  • 5
  • 0
  • 0
  • 0
AVERAGE RATING
NUMBER OF RATINGS
17

REVIEWS

  • Roshni Uppala
    Good start to System Verilog - Great concise course

    I really enjoyed taking this class. It is concise and very easy to follow. The instructor has definitely spent quality time in making this presentations effective. It gives you a good knowledge of testbenches, coding with system verilog. If you have basic verilog experience this a great place to start learning system verilog. I hope pdf's and more detailed explanation to the assignments would be provide shortly. The discussion forums are quick and you will pretty much get your reply soon. Enjoy !

  • Aneesh
    An excellent Introduction to Verification and SystemVerilog

    This course is an excellent introduction to Verification in general and also the SystemVerilog Language used for Verification. As a design engineer I learnt more about Verification and would be incorporating these concepts in my future projects. It is highly recommended to do the exercise given as it will clear many of your doubts. Mr. Ramdas has truly done a commendable job, which is not available in any other online Course Catalogs.

  • R Raval
    Good Tutorial on System Verilog

    Excellent Course

  • Venkat Naveen
    very good

    covers all concepts

  • Pratheep Joe Siluvai Iruthayaraj
    Excellent crash course on SV

    Quality material with good explanation and exercises