SOC Verification using SystemVerilog
4.3 (1,219 ratings)
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SOC Verification using SystemVerilog

A comprehensive course that teaches System on Chip design verification concepts and coding in SystemVerilog Language
4.3 (1,219 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
14,673 students enrolled
Last updated 5/2016
English
Price: Free
Includes:
  • 3.5 hours on-demand video
  • 1 Article
  • 7 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
Learn the important concepts in SOC/ASIC/VLSI design verification flow
Learn the System Verilog language for Functional Verification usage
Be ready and qualified for a Verification job in semiconductor industry
Udemy Certification on successful course completion
Be able to code, simulate and verify SystemVerilog Testbenches
View Curriculum
Requirements
  • Basic digital design or awareness to chip design flows
  • Passion for learning
Description

This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language - which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.

Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course

Who is the target audience?
  • Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry
  • Digital Design and Verification Professionals who are passionate about continuous learning
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Curriculum For This Course
Expand All 35 Lectures Collapse All 35 Lectures 04:15:06
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Welcome to Course - Introduction
3 Lectures 09:15

Brief introduction and overview of course - course goals, expectations, teaching methods etc.

Introduction and Overview
04:15

Introduces what is an SOC and what is a SOC/VLSI design flow is

Introduction to SOC and VLSI design flows
05:00

Course Resources
1 page

Testing Awareness before we start
4 questions
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Verification Concepts Explained
5 Lectures 51:50

Basic concepts of what is verification, why it is done and how it is done

Verification - What, Why and How ?
07:23

Explains concepts of verification plan, approaches, levels of verification and verification metrics

Verification - Planning, Approaches, Metrics
09:17

This lecture explains simulation based verification, Formal and Semi-Formal Verification and Assertion based Verification

Verification Methodologies - Simulation, Formal, Assertions
13:57

Explains and compares Directed vs Random Testing and Coverage Metrics and usage

Directed vs Constrained Random Verification - Coverage
12:59

Explains latest trends like Accelerated Simulation, Emulation and a wrap up Summary on this Section

Other Trends - HW+SW Verification, Emulation
08:14

Test your Verification Concepts now
5 questions
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Introduction to System Verilog Language
5 Lectures 42:59

Introduction to System Verilog language - History and evolution

History and Language usage overview
06:20

Basic design/TB structure and details on data types and operators in SV language explained

Language Constructs - Data types and Operators
10:41

Loops and Control flow related constructs explained - if/else, for/repeat/while, case/casex/z etc

Language Constructs - Loops and Control Flows
06:59

Explains System Verilog language support for subroutines - Tasks and Functions

Tasks and Functions
05:06

Explains SV support for Arrays (Fixed/Dynamic/Associative) and Queues

Arrays and Queues
13:53

Test Your System Verilog Language Basics now
5 questions
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Basic SV TB - Connecting to your design
4 Lectures 20:22

Explains the interface construct used for abstracting connectivity information between modules

Interfaces
08:40

Clocking blocks construct used for specifying timing information explained with examples

Clocking Blocks
05:26

Explains System Verilog Program Block Constructs

Program Blocks
06:16

System Verilog DPI explained. This alone is a presentation file with no video as of now. A video based lecture will be presented shortly

Direct Programming Interface (DPI)
4 pages

Test - How much more you know now !
4 questions
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SV - OOP concepts and Randomization
5 Lectures 47:52

General basic OOP concepts explains - inheritance, composition, polymorphism

Basic OOP Concepts
07:34

Explains Class definitions, Inheritance, polymorphism usage, const, static and abstract classes

System Verilog Classes Explained
15:01

Explains Virtual Interfaces and how it is used for connecting dynamic world of classes to static world of modules

Virtual Interfaces
07:35

Basics of creating random constraints in System verilog explained - simple randomness, simple constraints, implicaiton constraint, loop/array constraint etc

Random Constraints and usages - Part 1
09:42

Continuation of Random constraints - explains distribution constraints, layered constraints and a full example of how it is all used together

Random Constraints - Part 2
08:00

Test - What have you learned more now ?
5 questions
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Threads and Inter Process Communication
3 Lectures 21:57

Explains the concepts of processes and threads in System Verilog and how to implement those

Processes and Threads in System Verilog
06:22

Explains the concepts of System Verilog Mailboxes and its usages

System Verilog Mailboxes
06:50

Explains System Verilog Events and Semaphores implementation and usage in inter process handshake and synchronization

Synchronization - Events and Semaphores
08:45

Test your knowledge now on Advanced System Verilog
4 questions
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Project Assignment - Building a Testbench for Ethernet Switch
6 Lectures 09:08

A case study of applying all verification concepts learned so far to a real design verification problem

Exercise 1: Case Study on a Design to be verified
09:08

Here is an exercise for you to code a simple design using language constructs. We will use the same design in our future exercises to build a testbench around and to verify the same. Please discuss your solutions in comments section with the student community

Exercise 2: Coding exercise to build a Design to be Verified OR Review example
5 pages

In this exercise - create an interface for same design as in Exercise2 along with mod ports for monitor and driver and clocking blocks

Exercise 3: Coding Interfaces and Clocking Blocks to connect
2 pages

This is an exercise to start coding basic testbench components. Follow instructions. I will also convert this to a video lecture shortly

Exercise 4: Building Class based Testbench components
7 pages

Exercise to build remaining Test bench components and to extend previous components by implementing mailboxes

Exercise 5: Connecting all TB components using mailboxes
7 pages

Last exercise to build the top level testbench and instantiate all components

Exercise 6: Build the top TB with DUT, compile and simulate
6 pages
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Introduction to Verification Methodologies
2 Lectures 14:32

Explains the need and history of Industry standard verification methodologies

Standard Verification Methodologies - Need and evolution
08:17

Brief introduction to OVM/UVM methodologies and their highlights

Introduction to concept of OVM and UVM
06:15
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Course Wrapup and Summary
2 Lectures 05:12

Course wrap up summary and possible future course topics.Feel free to comment on the content or improvements required.

Also visit my new verification excellence school to learn about SVA and coverage and other upcoming courses

http://verificationexcellence.usefedora.com/

thanks

Ramdas

Summary and learnings and future topics
04:50

A short survey that helps me get feedback on what improvements can be made

Course Improvement Survey
00:22

Final Test - Are you ready for a Verification Job now?
2 questions
About the Instructor
Ramdas Mozhikunnath M
4.4 Average rating
1,873 Reviews
18,349 Students
3 Courses
Expert Verification Engr, Intel Alumni, 16+ yrs exp, Author

Expert and Passionate Verification Engineer with 16+ years of experience in design verification of complex Microprocessors, ASIC and SOC designs at major semiconductor companies like Intel, IBM and other exciting startups.

Co-Author of book "Cracking Digital VLSI Verification Interviews: Interview Success" available on Amazon

Passionate in continuous learning of new and interesting technologies and always ready to share knowledge and help others