Learn Vivado from Top to Bottom - Your Complete Guide
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Learn Vivado from Top to Bottom - Your Complete Guide

The complete guide for implementing designs on Xilinx FPGAs using Vivado Design Suite, for beginners and advanced users
Best Selling
4.8 (125 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
614 students enrolled
Created by Jordan Christman
Last updated 1/2017
English
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Includes:
  • 4 hours on-demand video
  • 12 Articles
  • 11 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Use Vivado confidently and proficiently.
  • Understand the steps required to take their FPGA design from start to finish.
  • Implement a micro blaze softcore processor on their FPGA.
  • Generate HDL designs from c based code, using Vivado’s high level synthesis tool.
View Curriculum
Requirements
  • Download and install Xilinx’s Vivado Design Suite, we will cover how to do this is the course if you are unsure of how to do so.
  • Understand or familiar with what an FPGA is and how they operate.
  • Interested in FPGA development and design.
Description

The Vivado design suite is the set of tools provided by Xilinx and is used to design, program, and debug Xilinx’s line of FPGAs. This course covers all of the different aspects and capabilities of the Vivado design suite. This course covers everything from the very basics to the more complex topics. This course is designed so that the student who has no experience with Vivado can take the course by starting with the very basics topics such as creating projects and design files. There are also more advanced topics so that the experienced student can learn things like how to create and program a soft core processor using the tools provided by Xilinx. This course covers many topics, including:

  • Downloading & Installing Vivado (I will be using a Windows machine, however you can install this on a Linux machine as well)
  • Creating Projects
  • Simulating Your Hardware Designs
  • Using Existing IP Cores
  • Creating & Managing Your Custom IP Cores
  • Creating and Programming a Micro Blaze soft core processor
  • Programming your Development Board
  • Automating Vivado Using Tool Command Line (tcl) Scripts
  • Creating Your Own Design Constraints
  • Converting Your C Code to a Hardware Design

Vivado contains many tools and this course will cover all of them, including:

  • Vivado's Hardware Manager - This is used to load the hardware designs onto the FPGA or on board memory.
  • Vivado's Simulator - This is what is used to simulate and verify that your design is working as expected.
  • Integrated Logic Analyzer (ILA)- This is used to act as a virtual oscilloscope while your design is running on the actual hardware target.
  • Vivado's High Level Synthesis - This tool read C based code and converts it to a HDL based design.
  • Xilinx's Software Development Kit (SDK) - This is the tool used to write C code that will run on the soft core processor implemented on the FPGA.

This course is laid out in such a way that each section takes on a specific topic or tool associated with Vivado. There are downloadable files that will have the students interact with Vivado so that they can get a hands on learning experience. The students will complete a hardware design project that will take them through all of the design steps neccasary so that they can start implementing their own idea's on Xilinx FPGAs using Vivado Design Suite. Vivado is a very powerful tool that has a lot to offer and this course is designed to help aid you in learning how to use this powerful tool.

Who is the target audience?
  • Anyone who works with Xilinx’s FPGAs.
  • Anyone who has an interest in understanding the tools used to implement designs on Xilinx FPGAs.
  • Altera based designers who would like to migrate to Xilinx based designs.
  • Makers who want to get started with FPGA development.
  • Students who are taking a course that requires FPGA design or development.
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Curriculum For This Course
70 Lectures
04:26:31
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Introduction
4 Lectures 13:04

This lecture introduces the course and explains everything that will be covered. This lecture also explains the course layout and what you can expect from this course.

Preview 02:00

This lecture introduces the Vivado Tool Suite and gives a quick summary of its capabilities.

Introduction to the Vivado Tool Suite
01:49

In this lecture you will see step-by-step how to download and install the Vivado design suite on your computer.

Preview 07:17

This lecture discusses the development boards and FPGA’s that are currently supported by Vivado.

Supported FPGAs and Development Boards
01:58
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Vivado Basics
11 Lectures 37:14

This lecture explains what you will see when you open Vivado for the first time.

Preview 02:50

This lecture will walk you through step-by-step on how to create a RTL project in Vivado. RTL projects are what we use to create designs we want to implement on the FPGA.

Preview 02:24

If there is a project that someone sends you that they created in Xilinx ISE, this lecture explains how to import that project and work on it inside of Vivado.

Importing a Xilinx ISE Project Into Vivado
03:52

This lecture walks through and shows students how to create a new project that is based off a predefined Vivado template.

Create a Project From a Predefined Template
02:34

This lecture shows how to access the example projects in Vivado. These projects are very useful for looking around and getting a better understanding of what can all be accomplished in Vivado.

Vivado Example Project
04:29

This lecture will walk you through how to add existing design files to your project. This is useful if you are developing the design in a separate program or received a design from someone else.

Preview 03:00

This lecture walks through the steps of creating new design files, simulation files, constraints files, etc… 

Creating New Files
04:10

In this lecture Vivado block designs are introduced and explained. You will walk through how to create them as well as use them to create your designs.

Working with Block Designs in Vivado
06:04

This lecture walks you through the required steps to create a bit stream file. This file is what is loaded onto your FPGA in order to configure it to operate as specified by your design.

Generating the FPGA Configuration File
03:45

This lecture shows where to find the FPGA configuration file and how to use Vivado’s Hardware Manager to locate and program your development board.

Programming Your Development Board
02:19

This lecture introduces Xilinx’s document navigator. Xilinx documentation navigator is an extremely powerful tool that allows you to find the most up to date documentation regarding all kinds of HDL/device specific topics.

Documentation Navigator
01:47
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Pin Planning Tool
6 Lectures 18:29

This lecture introduces Vivado’s pin planning tool and explains ways in which it can be used.

I/O Pin Planning Tool Introduction
01:55

In this lecture students are shown step-by-step how to create a pin planning project in Vivado.

Create an I/O Pin Planning Project
02:21

This lecture shows students how to create I/O ports and to place them on specific pins.

Create and Place I/O Ports
04:53

This lecture walks through the steps required to perform a design rules check on the pin placement selections.

Perform a Design Rules Check
01:35

This lecture shows how to check for simultaneous switching noise based on your pin placements.

Report Simultaneous Switching Noise SSN
03:29

In this lecture I will show you how to generate a constraints file based off your pin placement selections. I also will show you how this tool can create the top level HDL file for your design.

Generate Contraints File and Top Level HDL File
04:16
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Intellectual Property (IP) Cores
14 Lectures 01:04:53

In this lecture I will explain what an IP core is and how they are used when developing hardware. 

Introduction to IP Cores
04:46

In this lecture I will give a quick demonstration of why one would want to use IP cores over traditional Hardware Descriptive Language (HDL) programming.

Using IP Cores
02:55

This lecture shows step by step how to take hardware design files inside your Vivado project and turn them into IP cores. These IP cores can be placed in a block design inside Vivado.

Create IP Cores from a Specific Directory
06:45

This lecture explains how to create a custom IP core from a block design inside your Vivado project. This IP core can be saved into your custom IP core repository to be used again and again.

Create IP Cores from a Block Design
06:28

This lecture introduces the AXI interface and how it is used. We will use the AXI interface so that our IP cores can be controlled by the Micro Blaze softcore processor. We will actually use AXI IP cores in the “Working with Softcore Processor” section.

AXI Interface Explained
06:30

This lecture explains how to create an AXI IP core so that you can interface your IP core with a Micro Blaze soft core processor. The AXI IP cores can also be interfaced with the hard ARM cores located on Xillinx’s System on Chip (SoC) such as the Zynq.

Create an AXI IP Core Peripheral Step 1
02:54

This lectures walks through the steps of interfacing your HDL design with the AXI IP core generated HDL files.

Creating an AXI IP Core Peripheral - Step 2
12:39

This lecture walks through the steps of locating and placing your custom IP core with an AXI interface.

Create an AXI IP Core Peripheral Step 3
06:43

This lectures shows students how they can customize their IP cores. This lecture also shows how to attach a PDF document to their IP Core.

Customizing IP Cores
02:45

In this lecture I will walk through the steps required to create your own IP core repository. These custom IP Core repositories are nice because you can then reuse your designs from various projects.

Creating a Custom IP Core Repository
00:38

This lecture suggests different ways you can structure your IP core repository so that as you add more and more IP cores you can still stay organized.

IP Core Repository Directory Structure
00:41

At this point you know how to create your own IP cores from a block design, a specific directory, as well as creating IP cores with an AXI interface. In this lecture I am going to show you how to add IP cores to a specific repository.

Adding IP Cores to Your Repository
04:06

This lecture walks through the steps in how to add a IP core to your custom directory.

Adding a Custom IP Core Repository to a Vivado Project
02:08

This lecture talks about the types of maintenance that is required for an IP repository.

Managing a Custom IP Core Repository
04:54
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IP Core Design Examples
4 Lectures 17:55

This lecture shows step-by-step how to customize and initialize the FPGA’s internal block RAM using IP cores available through Vivado.

Configure Internal FPGA Block RAM (BRAM)
04:36

This lecture walks through the steps required to generate an external memory interface for your design. This is very useful when you plan on implementing a softcore processor or other memory heavy design.

Xilinx Memory Interface Generator (MIG) IP Core
07:03

When working with large designs and integrating soft/hard core processors, multiple AXI IP cores will likely be used. This lecture shows how to connect multiple of these IP cores to a single AXI master, which is usually a processor.

Connecting Multiple AXI Peripherals to a Single Master
02:44

Vivado has a neat tool that is useful for increasing productivity as well as keeping your block designs clean. In this lecture you will be shown how to utilize Vivado’s auto-router and regenerate your block designs.

Using Vivado's Connection Automation and Regerating Block Design Layouts
03:32
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Working with Design Constraints
3 Lectures 07:38

This is an introduction to design constraints, it explains what they are, were and how they are used. This lecture also explains what will be covered in this section.

What are Design Constraints
01:07

This lecture shows how to add I/O constraints to your design. I/O constraints include the logic level, physical pin location, as well as the type of signal implemented on the specified pin.

Applying I/O Constraints
03:15

Complex designs typically require multiple clocks running at different frequencies. This lecture shows how to add new clocks to your design at various frequencies.

Creating Clock Constraints
03:16
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Automating Vivado
5 Lectures 14:22

This lecture walks through and introduces as well as explains what a TCL script is and does. This is a powerful skillset to have as many other engineering tools use TCL scripts.

TCL Script Introduction
02:55

There are several ways to create a project in Vivado, the most straightforward being to use the new project wizard. However, if you are creating a lot of projects and they all are using the same parts / settings then creating a custom TCL will save a lot of time. In this lecture you will be shown step-by-step how to use TCL scripts to create a Vivado Project.

Build a Vivado Project Using TCL Scripts
03:32

This lecture shows how to create a block design, add IP cores to the newly created block design, and connect the IP cores all from a TCL script. These TCL scripts can be used again and again throughout different projects.

Populate a Block Design Using TCL Scripts
01:16

This lecture will show how to add custom TCL scripts to your IP core. These TCL scripts can then be used to add further customization to your IP cores.

Using TCL Scripts in Your Custom IP Core
03:17

When working with revision control software its ideal to have the smallest file sizes possible. Instead of checking in entire projects and generated files, it’s possible to only check in TCL scripts and source files. This lecture will show you how to generate a TCL script that will re-generate your project and block design.

How to Create Your Own Custom TCL Scripts
03:22
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Hardware Design Debugging and Verification
7 Lectures 38:02

This lecture discusses the required format of a test bench file for use in the Vivado Tool Suite. There are several example test benches included as well.

Creating Simulation Files (Test Benches)
03:59

In this lecture a step-by-step example is shown on how to simulate your design using Vivado’s internal simulation tool. This is a very powerful tool that can be used when trying to debug and verify your design prior to the actual implementation.

Simulating Your Designs in Vivado
04:01

This lectures shows ways to manipulate the simulated waveform for analysis. There are step-by-steps showing how to do the following:

- Zooming in/out or to a specific region
- Measuring time between signal edges
- Adding waves to the window
- Saving a waveform configuration file
- Change the format of a signal (radix)

Modifying the Simulation Waveform
07:06

While your troubleshooting / simulating your design using Vivado’s simulator you may need to generate inputs without having to modify the test bench. This lecture shows how to force an input or internal signal to a specified value to help aid in the debugging process.

Forcing Signal Values for Simulation
03:40

This lecture explains the different tools provided in the Vivado Tool Suite that are available to help you debug and verify that your design is working properly. Debugging hardware design is extremely challenging, but Vivado has some very powerful tools available to help you test and verify your design.

Vivado Debugging Tools Introduction
02:47

The Integrated Logic Analyzer Core is a logic analyzer that resides in your FPGA design while running. This core has many capabilities that an external logic analyzer would contain as well. In this lecture I am going to show you how to use the ILA debugging core.

How to Use the Integrated Logic Analyzer (ILA) Core for Debugging
09:01

The virtual I/O core is very useful for debugging designs; it can be used to see what is happening while your design is running. This is very useful because there are occasions when your simulation works but your design does not. In this lecture I am going to show you how to use the VIO debugging core.

How to Use the Virtual I/O (VIO) Core for Debugging
07:28
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Working with Soft Core Processors
2 Lectures 11:06

In this lecture we walk through the steps of creating a softcore processor project in Vivado. We will be using the MicroBlaze softcore processor.

Creating Your First Softcore Processor Project
05:27

This lecture walks through the steps of creating a basic softcore processor project. In this example we will be instantiating a MicroBlaze softcore processor in our FPGA. 

Add AXI Peripherals to Your MicroBlaze Processor
05:39
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High Level Synthesis Tool
1 Lecture 02:48

This lecture introduces Vivado’s High Level Synthesis tool, which is used to turn functional c code into a HDL design. This is a very powerful tool which can greatly speed up your development time. 

High Level Synthesis Tool Introduction
02:48
3 More Sections
About the Instructor
Jordan Christman
4.7 Average rating
860 Reviews
4,281 Students
9 Courses
Your FPGA Guy

Jordan Christman graduated from the University of Dayton with his Bachelor's degree in Electronic and Computer Engineering Technology. He also graduated from UD with his Master's degree in Electrical Engineering. Jordan currently has a patent pending for an electronic monitoring device. He has strong knowledge in FPGA (Field Programmable Gate Array) development, Digital Electronics, Circuit Board design, and VHDL design and modeling of hardware systems. Jordan's focus of study in school was embedded systems which involves circuit design, firmware development, implementation of computer hardware, and the interfacing of computer operating systems. Jordan's hobbies include mobile application development, layout and assembly of PCB's (Printed Circuit Boards), computer application programming, and anything related to electrical engineering.