Learn Verilog with Xilinx VIVADO Tool

Learn Verilog Programming from top to bottom with Xilinx VIVADO Design Suite for FPGA Development

Created byDigitronix Nepal

Last updated 3/2021

English

What you'll learn

Learn and understand about Verilog Programming Language
Verilog Design Flow and its Syntax/Semantics
Creating Basic Logic Gates in Verilog
VIVADO Design Flow for FPGA Design with Verilog
Understand Conditional Statement in Verilog
Combinational and Sequential Circuit Design with Verilog
Finite State Machine Design with Verilog
Structural Modeling/Design with Verilog

Course content

10 sections • 20 lectures • 4h 40m total length

Section 1a Introduction to Verilog and Basic Design with Verilog19:56
This Section is introduction verilog, verilog syntax, verilog revisions and Verilog design flow. we have introduced all the components of verilog program i.e module declaration, port declaration, assignment operation and end module in this section.
Section 1b Introduction to Verilog and Basic Design with Verilog13:43
This secction is continuation of previous section which consists of detail explanation of Module declaration, assign statement and port declaration in verilog. This lecture also consists of references/bibliography: books and links for verilog programming.
How to Download, Install VIVADO & Get 30 Day Evaluation License4:51
From this section you will know about how to download, install VIVADO and get 30 day evaluation license from xilinx.com.

VIVADO is state of art FPGA Design and Verification environment(IDE) which will allow you to design, test, verify and package your design for FPGA Market.
Section 1 Lab 1 Basic Logic Gate Design with VIVADO in Verilog19:47
This is first practical lab session in VIVADO Design suit, we have explained about the VIVADO GUI features, processes on VIVADO design environment. In this section we have created a very basic logic gate: and gate, we have created/viewed the RTL schematic and synthesized the Verilog program.
Section 1_0 How to Add Zybo Board Files in VIVADO [Optional]6:27
This lecture let you know about how to add zybo board on VIVADO, because of initiallly there is no zybo board in VIVADO you can only search zybo by parts (xc7z010clg400-1). After installing/adding zybo board files you can get zybo on board selection setting.

Section 2 Simulation with Verilog and Testbench Introduction11:11
This section explains about the creating testbench on verilog, components of testbench: DUT, instantiation stimulus. We also have included how to create testbench for basic logic gate:AND Gate.
Section 2 Lab 1 Design Simulation of AND OR Gate19:53
This is Lab session on Design and Simulation of AND Gate and then OR Gate. In this session we are going to design and create simulation testbench for AND gate and OR Gate. We have talk on how to write HDL code for Logic Gate and How to Create a Simulation testbench from scratch.

Section 3 Conditional Statement in Verilog Overview14:52
Conditional Statements are those statement which evaluates the condition, if the condition is true then expression_1 will executed else expression_2 will executed. There are different Conditional Statement in Verilog which are : "always block","if statement","case Statement". We also have talk on Looping structure in Verilog in this session.
Section 3 Lab 1 MUX 4:1 Design and Simulation16:11
This Session is Lab on MUX(4:1) Design and Simulation in Verilog with VIVADO Design Suit. From this lab you will know about the Always Block , Case Statement and MUX Design as well as Creating Simulation Waveform for MUX.

Requirements

Basics of Programming Language (C/C++ or any)
Basic Idea of Digital Design
We introduce Verilog from Very Basics so you don't need to Worry about Prerequisites!!!

Description

>>>This Course is crash course on Verilog Programming from Top to Bottom with Xilinx VIVADO Design suite<<<

Verilog is dominant Hardware Description Language or HDL for FPGA/ASIC/VLSI Design and Verification Market globally. It has around 50% of market share in global market . So getting idea of Verilog programming will be the plus point in your Resume for Job Application.

In this course we have introduced Verilog Programming in very simple manner so beginner who don't have any idea can get Verilog HDL idea from scratch to intermediate level.

We have Sections on Introduction and Basic Design with Verilog Programming, Simulation with Verilog and Creating Verilog Testbench, Conditional Statement in Verilog, Combinational Circuit Design with Verilog, Sequential Circuit Design with Verilog, Finite State Machine (FSM) Design and Structural Modeling with Verilog. All the Sections have Lab sessions which will done on VIVADO Design Suite.

VIVADO is State of Art FPGA Design environment from Xilinx which have great features of Designing HDL Projects, Synthesizing, Implementing the HDL Project and Generating Bitstream as well as Configuring the Project on FPGA. VIVADO has awesome features on Design/Resources Optimization, Static Timing Analysis and Performance Optimization etc.

So, having knowledge with Verilog and VIVADO take to you for best of best opportunities. Hurry Up and Join the Course!

Who this course is for:

Electrical Engineering
Computer Science
FPGA Design Enthusiast
Computer Engineering
Electrical and Electronics Engineering

Learn Verilog with Xilinx VIVADO Tool

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Course content

Introduction and Basic Design with Verilog and VIVADO5 lectures • 1hr 5min

Simulation with Verilog Testbench2 lectures • 31min

Section 3 Conditional Statement in Verilog2 lectures • 31min

Section 4 Combinational Circuit Design with Verilog1 lecture • 20min

Section 5 Sequential Circuit Design1 lecture • 20min

Section 6 Structural Design with Verilog2 lectures • 26min

8 bit ALU Design and Simulation on Verilog with Xilinx VIVADO1 lecture • 1min

Verilog Reference Guide (From Basics to Advance Verilog Design)1 lecture • 22min

Summary: Verilog Programming3 lectures • 1hr 2min

Conclusion2 lectures • 1min

Requirements

Description

Who this course is for: