A course that will help you learn everything about System Verilog Assertions (SVA) and Functional coverage coding which forms the basis for the Assertion based and Coverage Driven Verification methodologies. These are the two key methodologies used most widely in all current SOC/chip designs to ensure quality and completeness.
The course covers everything from concepts to coding along with several examples to illustrate as well as quizzes and lab exercises to make your learning thorough.
The course contents include several examples and illustrations from LRM and other popular books on SystemVerilog.
Welcome and Introduction to course
Introduction to Assertions - What is assertion and Why to use assertions, advantages and a brief history of how SVA evolved
Explains basic concepts of Immediate and Concurrent Assertions
Basic concepts of sequences and properties as building blocks to write complex assertions are explained
Sequence operators for cycle delay and repeat operators are explained
Explains the sequence operators - AND and OR, Intersect with examples
Explains the sequence operations first_match, throughout and within
Sequence opertors if..else conditions and .ended explained
Explaines usage of local variables and subroutines in sequences
Explains the usage of various sampled functions like $rose, $fell, $past, $stable etc
This lecture explains system tasks/function like $onehot/0, $isunknown, $assertoff/on/kill and usages with examples
Exercises for Sequences
Decribes the types of properties based on expressions or operators etc
Explains about recursive properties and how to use them
Explains multiple-clock assertions and also clock inference in single vs multiple clock assertions
Binding Assertions to Design and Usage of Expect blocks that are similar to assertions
Tips and Best practices while using Assertions
Exercises for assertions
Explains basic concepts of coverage, code vs functional coverage and why those are important
Explains basic concepts and syntax with examples for covergroup, coverpoint and Bins and how to use covergroups with arguments and inside classes
Explains more on bins, transition bins, automatic, wildcard, ignore and illegal
Explains cross coverage with examples
Explains the coverage options supported in System Verilog language
Explains predefined coverage methods , performance implications with coverage and cover properties
Summary and Wrap up
Expert and Passionate Verification Engineer with 16+ years of experience in design verification of complex Microprocessors, ASIC and SOC designs at major semiconductor companies like Intel, IBM and other exciting startups.
Co-Author of book "Cracking Digital VLSI Verification Interviews: Interview Success" available on Amazon
Passionate in continuous learning of new and interesting technologies and always ready to share knowledge and help others