The Verification industry is adopting SystemVerilog based UVM Methodology at a rapid pace for most of the current ASIC/SOC Designs and is considered as a key skill for any job in the front end VLSI design/verification jobs.
This course teaches
Welcome and Introduction to the Course
Explains the need for Verification methodology and also about What a methodology should provide
Explains the concepts of Layered Testbench architecture and the benefits of modularity and re-usability of them in Verification industry
Explains the concepts of what is meant by Factory in OVM and UVM and how Factory concept can be used to dynamically create various components and sequences
Explains what is OVM, UVM and some of the highlights and differences. Since UVM evolved from OVM - most of the concepts remain same and so does coding
OVM and UVM are built on top of Transaction level Modelling concepts and hence important to understand the basics of TLM concepts
The different ways to communicate on a TLM channel for the higher layer components - What are ports and exports and how those are connected?
Explains Analysis ports and Analysis FIFOs and how they are used for TLM communication?
Code and simulate a simple TLM example on edaplayground and make your concepts thorough
Learn the concepts of how a OVM/UVM based Testbench Architecture looks like and what the different components are
Understanding concepts of UVM Sequencer and Driver components and how to implement them
Understand how Sequencers and Drivers communicate on TLM interface and how to connect TLM ports and exports for driver and Sequencer
Understanding concepts of a UVM Monitor component and how to implement a monitor component
Understanding the concepts of OVM/UVM Agents and how to implement Agent Components
Understand the conepts of UVM environment and Test class and how to hierarchicaly organize components inside an environment and Test class
Understanding the importance of simulation phases and the different simulation phases in OVM and UVM - namely the build, connect and run phases
Test your learning about testbench components and hierarchy
Explains what is the concept behind Stimulus generation using Sequences? What are Sequences and how they can generate flexible stimulus
Explains what is a sequence item and how to implement a sequence item. What are all the methods/API that a OVM/UVM Sequence item supports?
Explains the concepts of Sequences and the different Methods/API associated with Sequence like start(), body() etc
All Sequences are send to target driver through Sequencer. This lecture explains the communication mechanism used by Sequencer and Driver to connect and talk through the TLM interface
Explains the different ways possible for generating sequences. Sequences can be generated sequentially or parallely or in a layered manner and other ways thus providing flexible and efficient stimulus generation
Explains the concept of Virtual Sequence and why virtual sequences are important along with few examples
Explains the concepts of OVM and UVM configuration objects and how those can be used
Coming Soon. This will be video lecture available by November 1 2014
Overview about assignment - Implementing a complete UVM environment for AMBA APB Protocol
Explains the details of the APB(Advanced Peripheral Bus ) Protocol and the interface signals and how the read and write transactions are on APB bus
Architecting testbench for APB protocol following UVM concepts. Block diagram and explanation of different testbench components and stimulus/sequences
Explains how to create a basic APB Transaction or sequence item.
Explains how to define the interface file for APB protocol and the modports and clocking blocks to implement
Explains how to code and implement the APB Driver and Sequencer component
Explains how to code and implement an APB monitor component
Explains how to create the APB Agent and Env Components
Explains how to create different sequences that can be used to stimulate the APB interface with different transactions
Building Top level Test class, Test module and how to start sequences.
Also explains how to run simulation and what to observe in terms of transactions seen by driver and monitor
Summary of key concepts and a preview of topics for learning Advanced UVM concepts
Expert and Passionate Verification Engineer with 16+ years of experience in design verification of complex Microprocessors, ASIC and SOC designs at major semiconductor companies like Intel, IBM and other exciting startups.
Co-Author of book "Cracking Digital VLSI Verification Interviews: Interview Success" available on Amazon
Passionate in continuous learning of new and interesting technologies and always ready to share knowledge and help others