Learn to build OVM & UVM Testbenches from scratch

Learn and Start building Verification Testbenches in SystemVerilog based Verification Methodologies - OVM and UVM

Created byRamdas Mozhikunnath M

Last updated 7/2015

English

What you'll learn

Understand concepts behind OVM and UVM Verification methodologies
Start coding and build testbenches using UVM or OVM Verification methodology

Course content

7 sections • 36 lectures • 5h 27m total length

Introduction to Course3:33
Welcome and Introduction to the Course
Need for Verification Methodologies13:58
Explains the need for Verification methodology and also about What a methodology should provide
Layered Testbench Architecture - Concepts and Importance14:56
Explains the concepts of Layered Testbench architecture and the benefits of modularity and re-usability of them in Verification industry
Download Course Resource And Assignment Instructions2:00
Explains the concepts of what is meant by Factory in OVM and UVM and how Factory concept can be used to dynamically create various components and sequences

Introduction to OVM, UVM Concepts7:12
Explains what is OVM, UVM and some of the highlights and differences. Since UVM evolved from OVM - most of the concepts remain same and so does coding
Transaction Level Modelling Basics15:01
OVM and UVM are built on top of Transaction level Modelling concepts and hence important to understand the basics of TLM concepts
TLM Interfaces - Ports and Exports, FIFOs15:01
The different ways to communicate on a TLM channel for the higher layer components - What are ports and exports and how those are connected?
TLM Interfaces - Analysis Ports and FIFOs3:41
Explains Analysis ports and Analysis FIFOs and how they are used for TLM communication?
Test your basics on Transaction Level Modelling
Assignment 1 : Producer Consumer Example Code Simulation7:32
Code and simulate a simple TLM example on edaplayground and make your concepts thorough

Testbench Components and Hierarchy14:59
Learn the concepts of how a OVM/UVM based Testbench Architecture looks like and what the different components are
Building Driver and Sequencer Components13:53
Understanding concepts of UVM Sequencer and Driver components and how to implement them
Sequencer to Driver Connection11:34
Understand how Sequencers and Drivers communicate on TLM interface and how to connect TLM ports and exports for driver and Sequencer
Building a Monitor Component8:00
Understanding concepts of a UVM Monitor component and how to implement a monitor component
Building an Agent Component9:58
Understanding the concepts of OVM/UVM Agents and how to implement Agent Components
Environment and Test Class Components9:53
Understand the conepts of UVM environment and Test class and how to hierarchicaly organize components inside an environment and Test class
Building and Connecting Testbench Components15:01
Explains about how the different testbench components are build and connected in OVM/UVM
Understanding Simulation phases13:23
Understanding the importance of simulation phases and the different simulation phases in OVM and UVM - namely the build, connect and run phases
Test your concepts on Testbench Components

Basics of Sequence based Stimulus Generation14:27
Explains what is the concept behind Stimulus generation using Sequences? What are Sequences and how they can generate flexible stimulus
Sequence Items and Methods15:01
Explains what is a sequence item and how to implement a sequence item. What are all the methods/API that a OVM/UVM Sequence item supports?
Sequences and its Methods15:01
Explains the concepts of Sequences and the different Methods/API associated with Sequence like start(), body() etc
Sequencer and Driver API14:45
All Sequences are send to target driver through Sequencer. This lecture explains the communication mechanism used by Sequencer and Driver to connect and talk through the TLM interface
Sequence Generation Styles8:13
Explains the different ways possible for generating sequences. Sequences can be generated sequentially or parallely or in a layered manner and other ways thus providing flexible and efficient stimulus generation
Basics of Virtual Sequences7:28
Explains the concept of Virtual Sequence and why virtual sequences are important along with few examples
Test your basics on Sequence based Stimulus generation

Assignment Overview5:14
Overview about assignment - Implementing a complete UVM environment for AMBA APB Protocol
Introduction to APB Protocol8:48
Explains the details of the APB(Advanced Peripheral Bus ) Protocol and the interface signals and how the read and write transactions are on APB bus
APB Testbench Architecture5:05
Architecting testbench for APB protocol following UVM concepts. Block diagram and explanation of different testbench components and stimulus/sequences
Creating APB Transaction and Interface3:33
Explains how to create a basic APB Transaction or sequence item.

Explains how to define the interface file for APB protocol and the modports and clocking blocks to implement
Creating APB Driver and Sequencer2:33
Explains how to code and implement the APB Driver and Sequencer component
Creating APB Monitor2:09
Explains how to code and implement an APB monitor component
Creating APB Agent And Env3:04
Explains how to create the APB Agent and Env Components
creating Sequences2:16
Explains how to create different sequences that can be used to stimulate the APB interface with different transactions
Building Test, Top Module and Simulating your test4:40
Building Top level Test class, Test module and how to start sequences.

Also explains how to run simulation and what to observe in terms of transactions seen by driver and monitor
Summary6:48
Summary of key concepts and a preview of topics for learning Advanced UVM concepts

Requirements

Basic understanding of Functional Verification concepts
Basic understanding of SystemVerilog and object oriented concepts
Motivation to learn and discuss questions in the Forums

Description

The Verification industry is adopting SystemVerilog based UVM Methodology at a rapid pace for most of the current ASIC/SOC Designs and is considered as a key skill for any job in the front end VLSI design/verification jobs.

This course teaches

Basic concepts of two (similar) methodologies - OVM and UVM -
Coding and building actual testbenches based on UVM from grounds up.
Plenty of examples along with assignments (all examples uses UVM)
Quizzes and Discussion forums
Hands on assignment to build a complete UVM Verification environent for a most popular SOC Bus protocol - APB Bus

Who this course is for:

Verification engineers who have basic understanding of SystemVerilog but new to OVM/UVM methodology
Students passing out of VLSI/DigitalDesign/Microelectronics looking for a job in front end of VLSI design
Any VLSI front end design/verification engineer who wants to increase their job opportunities and skills

Learn to build OVM & UVM Testbenches from scratch

What you'll learn

Explore related topics

Course content

Introduction and Welcome4 lectures • 34min

Fundamentals of OVM/UVM - Transaction Level Modelling5 lectures • 48min

Building Testbench Components8 lectures • 1hr 37min

Sequence Based Stimulus Generation6 lectures • 1hr 15min

Dynamic Construction and Configurations3 lectures • 29min

Assignment - Building and Simulating APB (Advanced Peripheral Bus) Testbench10 lectures • 44min

Summary and Preview of Advanced Topics for Further Study0

Requirements

Description

Who this course is for: