This course was designed to give students an opportunity to kick-start their skills to Design Digital Electronics WITHOUT the hurdle of having to code in HDL.
How this course works
Concepts are first explained, then demonstrated by using the ISE software from Xilinx. Coding in HDL languages will not be taught in this course but instead, Schematics will be used as it is easier for beginners. Students will only need drag, drop and connect schematic symbols together. Then Run through the flow of ISE to generate the bit file.The bit file will be downloaded on the board to see the results.
The goal is to quickly put together designs and try them on the board, without the hurdle of VHDL/Verilog coding. In this way, you will focus on how Digital Electronics works.
This course doesn't show software simulation but focuses on testing your designs straight on the board.
What will you need?
You will need to download and install Xilinx ISE software in the Webpack version, which is free. Ideally you will need the Basys 2 board, which uses the Spartan 3E FPGA, to verify your design on hardware.
The course is split in sections of the main building blocks of Digital Electronics such as Registers, Logic Gates, Random Access memory etc...
In each section there is explanation of various blocks e.g in the Registers section will be explained the Flip Flops and Shift Registers. After most blocks explanation there will be a practical activity on how to implement the circuit on an FPGA and verify the design on the Basys 2 board.
There is a generous number of quizzes between the lessons to help the students keep focused and find the course fun to undertake.
Most of the Practical Activities will be simply to load the design on your Basys2 board and use the switches as input & LEDs as output. Additionally, at the end of the course, you will also learn how to connect the board to other external components using JTAGs through the use of wires and a breadboard.
This lesson will show you the steps to download and install ISE on your machine. You will have to go to download section of Xilinx.com and download ISE 14.7. This is the last version of ISE which support Schematic Design entry. Once ISE Webpack is installed, you will need a license to use the software.
You will learn how to get a free license for ISE Webpack. This will allow you to use ISE perpetually for certain devices, including that on the Basys2 board. This license allows the use of the full flow of ISE.
Since you will use ISE in this course, it's good idea to know how to get around in the Project Navigator. You will learn how to open, save, add new sources, create a new course, archive etc...
This lecture will show the typical gates used in digital electronics and they are:
This lesson shows how to implement a single logic gate, which is the XOR on the board. It will be a very simple design with one gate and ports. Once loaded on the board, you will be able to test it using LEDs.
In this lesson we will see how to implement a more complex design made up of multiple interconnected gates. The design will be implemented on the board and will use the switches for input and the LEDs to indicate output.
Registers or Flip Flops are important building blocks in digital circuitry. They are mainly used to store information in the form of bits. Most Flip flops will be used synchronously with the clock. In this lesson we will implement a simple FF on the board.
In this lesson you will learn how to use a basic Data FF on an FPGA. You will see how it works on hardware.
We will introduce the concept of Clear and Enable in relation Flip Flops (FF). If a flip flop has a clear pin, a HIGH value will normally clear the state of the FF to ZERO. When the clear pin is LOW, it will have no effect on the FF and so it would work normally.
Enable line is to enable to FF to work normally (when Enable=1) or stay unaffected by the clock (when Enable = 0).
Shift Registers are useful piece of circuitry for buffering data, pipelining and more. We will connect individual Flip Flops to build a Shift Register and see it work on hardware by shifting some data in.
Since a push button is slow, push it down will create a pulse of several period cycles. A debouncer circuit has the job of outputting a single pulse from a push button. It consists of three registers and ANDED outputs.
In this project will add a debouncer circuit as a symbol and use it to feed the Chip Enable of the Shift Register (SR). This will allow us to see the shifting of bits into the SR by pushing the push button on our board.
Using selector lines of Multiplexers can allow specific input to go through the multiplexer in real time on hardware. If the number of selector bits are n, then the number of input lines would be 2 power n e.g 3 bits selector will control up to 8 input lines
You will see how to Implement a simple Multiplexer on the FPGA Board. You will use the Mux to select which input will go through to the output using selectors.
In this lesson you will learn the concept of Binary Counter. In the binary world, numbers are only represented with 1 and 0's.
In this lesson you will learn how to build a basic counter easily and see it increment using LED's on the board
The Xilinx Symbol Library has adders and subtractors that can be used to add/subtract two numbers in binary.
We will implement a simple adder on the FPGA using binary numbers. We will verify the adder on hardware against a calculator.
RAM's are Random Access Memories used to store temporary data. The data in the RAM is volatile and so cannot be stored when the power is off on the board. You will learn about the normal connections to a RAM and how are data structured in it.
In this lesson we will implement a RAM on hardware, store some data, then retrieve the data when needed.
It is common to use states to define an electronic system. For example: an alarm can be in a state of 'no alarm' or 'alarm' or 'stand by' etc...State Machines are very useful piece of electronic circuitry used to store information about States. In this lesson you will learn how to describe and design state machines.
There are two main types of States Machines: (1) Mealy and (2) Moore.
In this lesson we will implement the state machine that we described in the previous lesson on an FPGA. We will check how the state changes with different sequence of input.
In this lesson, the State Transition Table will be derived and explained
From the truth table, the Transition and Output Logic will be designed and we will confirm that the derived logic match that of the project for this alarm.
Ajmir has been an electronics/programming/science hobbyist since the age of 12 and obtained his Bachelor in Electronics and Communication Engineering from the University of Mauritius in the year 2001.
After graduation he attended a short course in Web Design, where he learned HTML, PHP and Java.
He has worked at various positions in the Electronics Industry, including Sales Engineer for electronic instruments, Lecturing in Power Electronics and Data Communication, Test Engineer and Debugging boards for UK Road Signs.
Ajmir worked for nearly 7 yrs at Xilinx in Dublin, Ireland as a Product Applications Engineer, supporting Xilinx FPGA Design Automation Software tools. He became a specialist in Synthesis tools/Timing Analysis at Xilinx. He also worked with Digital Signal Processing on FPGA. While at Xilinx he had the chance to meet very interesting people in the industry and attended various courses. He was privileged to have provided support to major companies in the Electronics Industry and has been in touch with real life electronics designs.
Since 2013 he got curious and grew interested in building commercial Online Applications and completed a BSc in Digital Technology at the Digital Skills Academy in Dublin.
Ajmir is interested in Mathematical Modelling, Science, Arts and Philosophy.
He is passionate about imparting knowledge to others.