Introduction to VHDL
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Introduction to VHDL

Understand VHDL and how it is used to describe digital circuits
4.7 (20 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
108 students enrolled
Created by Jordan Christman
Last updated 8/2017
English
Current price: $10 Original price: $50 Discount: 80% off
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Includes:
  • 4.5 hours on-demand video
  • 17 Articles
  • 22 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Implement their own VHDL designs on a FPGA / CPLD
  • Interpret a digital design written in VHDL
  • Simulate their own VHDL designs
View Curriculum
Requirements
  • You should have a basic knowledge of digital logic gates
  • You should be comfortable with using a computer
  • Download & install Vivado (the link is provided in the course)
  • Download & install ModelSim (the link is provided in the course)
Description

Introduction to VHDL is a course that someone with no experience or knowledge of VHDL can use to learn and understand the VHDL language. In this course students will learn about all of the different data types associated with the VHDL language. This course focuses on teaching students how the syntax of VHDL is interpreted and how it can be used to design circuits. There are over 8 different examples digital designs implemented in VHDL.

Course Structure

This course starts out by explaining the background and history of VHDL and it's uses. Then students will learn about all the different objects and data types associated with VHDL. There are various examples showing the data types in use and how different objects behave in different applications. After learning about the data types and objects, students will then learn about the keywords and syntax of the VHDL language. Then students will learn about all of the different design architectures used in VHDL. Students will also learn how to design a test bench to simulate and verify functionality of their designs. This knowledge will then be used to complete the final project, tying in all facets of the VHDL language.

VHDL Designs

This course has many design examples, upon completing this course students will have their own library of VHDL design they can use and refer to at any time! This design library includes:

  • Logical AND gate
  • Logical OR gate
  • Logical NOR gate
  • Logical NAN gate
  • Logical XOR gate
  • Half Adder
  • Full Adder
  • D Flip-Flop
  • Digital Comparator
  • SR (Set Reset) Latch
  • 2:1 Multiplexer
  • Priority Encoder

Final Project

The final project in the course has students go through the design process of implementing a priority encoder on their very own development board. This project takes students through the various phases of developing a digital design, testing it, and implementing it. Students will be taken through step-by-step everything that is required to get the priority encoder up and running on their development board.

Feel free to message me with any questions before signing up for this course!

Who is the target audience?
  • Anyone who wants to understand VHDL
  • Anyone who wants to create their own VHDL designs
  • Anyone who wants to implement designs inside an FPGA or CPLD
  • Anyone who wants to know how to simulate digital designs using VHDL
  • Electrical engineers
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Curriculum For This Course
54 Lectures
06:13:12
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Introduction
3 Lectures 09:52

In this lecture I introduce myself as well as what you can expect to learn from this course.

Preview 05:02

This lecture discusses the background of VHDL and ways it can be used.

Background
01:51

This lecture shows an example of a way in which you can use VHDL, to simulate digital circuits.

Preview 02:59
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Objects
7 Lectures 24:48

This lecture introduces the concept of VHDL objects amd the various objects that are used in the VHDL language.

Objects
01:05

This lecture discusses and explains what signals are in the VHDL language.

Signals
02:14

This lecture gives an example of how signals are used in VHDL.

Signal Example
06:32

This lecture discusses variables and how they are used in the VHDL language.

Variables
01:47

This lecture gives an example of VHDL variables being used.

VHDL Variable Example
08:03

This lecture covers constants in the VHDL language and gives an example of how to use them.

Constants
01:19

This lecture discusses how files can be used in VHDL.

Files
03:46
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Data Types
4 Lectures 01:49:43

This lecture talks about the standard logic 1164 package and the data types and operations it supports.

Standard Logic 1164
26:25

This lecture talks about the standard logic text IO package and the operations it supports.

Standard Logic Text IO Package
02:04

This lecture discusses the standard logic arithmetic package.

Standard Logic Arithmetic
35:50

This lecture describes and explains how the Numeric Bit package is used in VHDL.

Numeric Bit
45:22
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Loops and Statements
5 Lectures 11:34

This lecture discusses the format of IF statements in VHDL and how they are processed.

IF Statement
02:28

This lecture discusses how CASE Statements are used in VHDL and how they are processed.

CASE Statement
01:54

This lecture explains two common loops used in VHDL:

  • While Loops
  • For Loops

Examples are given to show how these loops are constructed and operate.

LOOP Statement
03:16

This lecture explains how the NEXT statement is used in the VHDL language.

NEXT Statement
01:14

This lecture explains the VHDL EXIT statement and gives examples of the the EXIT statement being used.

EXIT Statement
02:42
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Design Structure
4 Lectures 21:55

This lecture shows an example of defining an entity in VHDL. This examples uses a digital logic circuit as an example.

Entity Example 1 - Digital Logic Circuit
04:32

This lecture walks through the steps of defining an entity for a multiplexer.

Entity Example 2 - Multiplexer
04:58

This lecture walks through the example of defining the architecture of a digital logic circuit.

Architecture Example 1 - Digital Logic Circuit
05:46

This lecture walks through an example of defining the architecture for a multiplexer.

Architecture Example 2 - Multiplexer
06:39
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Data Flow Design Style
5 Lectures 25:47

This lecture shows examples of various logic gate implementations in VHDL, including:

  • AND gate
  • OR Gate
  • NAND Gate
  • NOR Gate
  • XOR Gate
  • XNOR Gate

Upon completing this lecture students will be gain a better understanding of how to implement a digital design using VHDL.

Logic Gate VHDL Implementations
02:15

This lecture takes you through and shows step-by-step how to define an AND gate using VHDL.

Preview 07:00

This lecture takes you through and shows step-by-step how to define an AND gate using VHDL.

OR Gate VHDL Design
03:00

In this lecture you will see step-by-step and line by line how a half adder is design in VHDL using a data flow style of architecture.

Half Adder Data Flow Design
05:33

In this lecture you will see step-by-step and line by line how a full adder is design in VHDL using a data flow style of architecture.

Full Adder Dataflow Design
07:59
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Behavioral Design Style
3 Lectures 33:23

In this lecture you will see step-by-step and line by line how a full adder is design in VHDL using a behavioral style of architecture.

Full Adder Behavioral Design
12:25

In this lecture you will see step-by-step and line by line how a D flip-flop is design in VHDL using a behavioral style of architecture.

D Flip-Flop Behavioral Design
11:46

In this lecture you will see step-by-step and line by line how a comparator is designed in VHDL using a behavioral style of architecture.

Comparator Behavioral Design
09:12
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Structural Design Style
3 Lectures 28:12

In this lecture you will see step-by-step and line by line how a full adder is design in VHDL using a structural style of architecture.

Full Adder Structural Design
10:16

In this lecture you will see step-by-step and line by line how a SR latch is designed in VHDL using a structural style of architecture.

Set-Reset Latch Structural Design
08:39

This lecture walks through the entire design process for creating a 2:1 Multiplexer in VHDL. This design uses the structural style of architecture.

2:1 Multiplexer Structural Design
09:17
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Test Bench Designs
2 Lectures 31:45

IN this lecture a full adder test bench is designed. This test bench is designed to be used with a simulator to simulate a full adder design.

Full Adder Test Bench Design
14:03

This lecture walks through a test bench designed for a D flip-flop. This test bench is then designed to be used with a simulator to test the D flip-flop design.

D Flip-Flop Test Bench Design
17:42
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Simulations
8 Lectures 44:07

This lecture walks through and shows how to simulate your AND gate VHDL design using ModelSim.

AND Gate ModelSim Simulation
04:22

This lecture walks through and shows how to simulate your AND gate VHDL design using Vivado.

AND Gate Vivado Simulation
08:24

This lecture walks through and shows how to simulate your OR gate VHDL design using ModelSim.

OR Gate ModelSim Simulation
04:01

This lecture walks through and shows how to simulate your OR gate VHDL design using Vivado.

OR Gate Vivado Simulation
05:05

This lecture walks through and shows how to simulate your D flip-flop VHDL design using ModelSim.

D-Flip Flop ModelSim Simulation
03:20

This lecture walks through and shows how to simulate your D flip-flop VHDL design using Vivado.

D Flip-Flop Vivado Simulation
07:52

This lecture walks through and shows how to simulate your full adder VHDL design using ModelSim.

Full Adder ModelSim Simulation
02:57

This lecture walks through and shows how to simulate your full adder VHDL design using Vivado.

Full Adder Vivado Simulation
08:06
2 More Sections
About the Instructor
Jordan Christman
4.7 Average rating
929 Reviews
4,582 Students
9 Courses
Your FPGA Guy

Jordan Christman graduated from the University of Dayton with his Bachelor's degree in Electronic and Computer Engineering Technology. He also graduated from UD with his Master's degree in Electrical Engineering. Jordan currently has a patent pending for an electronic monitoring device. He has strong knowledge in FPGA (Field Programmable Gate Array) development, Digital Electronics, Circuit Board design, and VHDL design and modeling of hardware systems. Jordan's focus of study in school was embedded systems which involves circuit design, firmware development, implementation of computer hardware, and the interfacing of computer operating systems. Jordan's hobbies include mobile application development, layout and assembly of PCB's (Printed Circuit Boards), computer application programming, and anything related to electrical engineering.