This System Verilog course teaches the digital IC and ASIC design techniques used in VLSI industry. It covers the basics of digital design techniques and teaches the basic concepts of using a hardware description language like System Verilog (SV) for IC design.
This course contains video lectures of 1 hour 45 minutes duration. It is stared by explaining a brief history of ICs and evolution of hardware description languages. The starting point learning System Verilog, "writing the first module" is explained here next. The remaining sessions of this course teaches you the SV language constructs, types of modelling and some illustrative examples. Implementation of sequential and combination digital circuits are explained in detail which will help the learner to grab the difficult ideas in using 'assign' & 'always' and 'blocking'& 'non-blocking assignments' in SV.
By taking this course, the a student will be able to start digital design using Verilog or System Verilog and master it slowly. This course will also be helpful for the SV programmers who know how to write an SV program but not clear about how they actually get implemented to a hardware.
A post graduate in electronics engineering with 8+ years of experience in ASIC design & verification using system-verilog with major semiconductor companies like Intel India and ARM UK. A passionate and continuous learner in emerging VLSI methodologies. Enjoys learning new technologies and sharing knowledge.