SystemVerilog Design: Start Programming Your Own ICs in HDL

VLSI : Verilog / System Verilog for SOC Design - Map digital circuits to HDL programs & begin RTL coding
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998 students enrolled
Instructed by Ajith Jose IT & Software / Hardware
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  • Lectures 14
  • Length 2 hours
  • Skill Level All Levels
  • Languages English
  • Includes Lifetime access
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    Available on iOS and Android
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About This Course

Published 8/2015 English

Course Description

This course teaches the digital IC and ASIC design techniques used in VLSI industry using System Verilog language. It covers the basics of digital design techniques and teaches the basic concepts of using a hardware description language like System Verilog (SV) for IC design.

This course contains video lectures of 1 hour 45 minutes duration. It is stared by explaining a brief history of ICs and evolution of hardware description languages. The starting point learning System Verilog, "writing the first module" is explained here next. The remaining sessions of this course teaches you the SV language constructs, types of modelling and some illustrative examples. Implementation of sequential and combination digital circuits are explained in detail which will help the learner to grab the difficult ideas in using 'assign' & 'always' and 'blocking'& 'non-blocking assignments' in SV.

By taking this course, the a student will be able to start digital design using Verilog or System Verilog and master it slowly. This course will also be helpful for the SV programmers who know how to write an SV program but not clear about how they actually get implemented to a hardware.

What are the requirements?

  • There are no prerequisites for this course but it is good to know basics of Digital circuits and programming in any language.

What am I going to get from this course?

  • Write System-Verilog RTL programs for designing ASICs and Digital ICs
  • Understand the technical background of complex digital ICs

What is the target audience?

  • This System-Verilog course will be an ideal starting point towards learning RTL coding for Digital ICs and ASICs. The intended audience are students and professionals who are NOT experts in Verilog or System-Verilog IC design
  • This course is designed for beginer and intermdeidate level learning of System-Verilog and may not be an ideal for those who are experts in it.
  • Also, this course covers the design aspects of System-Verilog programming and NOT the verification part of it. Thus if you are keen to learn System-Verilog for RTL verification, this is not an ideal one. But it is highly recommended to understand concepts of RTL design before you start verification on it.

What you get with this course?

Not for you? No problem.
30 day money back guarantee.

Forever yours.
Lifetime access.

Learn on the go.
Desktop, iOS and Android.

Get rewarded.
Certificate of completion.

Curriculum

Section 1: Introduction
Introduction
Preview
06:38
Section 2: Introduction to HDLs
Introduction to System Verilog
Preview
10:33
Section 3: Language Constructs
Language Constructs -1
09:11
Language Constructs -2
06:02
Section 4: Transistor Level, Gate Level and Behavioral Modeling in SV
Types of Modelling
05:49
Section 5: Modelling Sequential and Combination Circuits
Simulation And Synthesis
03:17
Assign and Always Statements
06:10
Blocking and Non-blocking Assignments
10:18
Section 6: Examples of RTL coding
Illustrative Examples
06:20
Section 7: Modules
Modules in detail
12:20
Section 8: Start Simulating
Design and Test Bench
12:28
TB for Combination Circuit
04:22
TB for Sequential Circuit
07:56
Section 9: Summary
Summary
07:18

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Instructor Biography

Ajith Jose, Hardware Engineer

A post graduate in electronics engineering with 8+ years of industrial experience in ASIC design and Verification using System Verilog at major semiconductor companies. A passionate and continuous learner in emerging technologies in VSLI and also interested in other technical domains related to programming. Finds energy in learning new technologies and and sharing knowledge with others.

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