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SystemVerilog Design: Start Programming Your Own ICs in HDL

VLSI : Learn Verilog / System Verilog for SOC Design - Map digital circuits to HDL programs & begin RTL coding
3.9 (64 ratings)
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1,046 students enrolled
Created by Ajith Jose
Last updated 9/2015
English
$15 $40 62% off
30-Day Money-Back Guarantee
Includes:
  • 2 hours on-demand video
  • 1 Supplemental Resource
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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Description

This System Verilog course teaches the digital IC and ASIC design techniques used in VLSI industry. It covers the basics of digital design techniques and teaches the basic concepts of using a hardware description language like System Verilog (SV) for IC design.

This course contains video lectures of 1 hour 45 minutes duration. It is stared by explaining a brief history of ICs and evolution of hardware description languages. The starting point learning System Verilog, "writing the first module" is explained here next. The remaining sessions of this course teaches you the SV language constructs, types of modelling and some illustrative examples. Implementation of sequential and combination digital circuits are explained in detail which will help the learner to grab the difficult ideas in using 'assign' & 'always' and 'blocking'& 'non-blocking assignments' in SV.

By taking this course, the a student will be able to start digital design using Verilog or System Verilog and master it slowly. This course will also be helpful for the SV programmers who know how to write an SV program but not clear about how they actually get implemented to a hardware.

Who is the target audience?
  • This System-Verilog course will be an ideal starting point towards learning RTL coding for Digital ICs and ASICs. The intended audience are students and professionals who are NOT experts in Verilog or System-Verilog IC design
  • This course is designed for beginer and intermdeidate level learning of System-Verilog and may not be an ideal for those who are experts in it.
  • Also, this course covers the design aspects of System-Verilog programming and NOT the verification part of it. Thus if you are keen to learn System-Verilog for RTL verification, this is not an ideal one. But it is highly recommended to understand concepts of RTL design before you start verification on it.
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What Will I Learn?
Write System-Verilog RTL programs for designing ASICs and Digital ICs
Understand the technical background of complex digital ICs
View Curriculum
Requirements
  • There are no prerequisites for this course but it is good to know basics of Digital circuits and programming in any language.
Curriculum For This Course
Expand All 14 Lectures Collapse All 14 Lectures 01:48:42
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Introduction
1 Lecture 06:38
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Introduction to HDLs
1 Lecture 10:33
+
Language Constructs
2 Lectures 15:13
Language Constructs -1
09:11

Language Constructs -2
06:02
+
Transistor Level, Gate Level and Behavioral Modeling in SV
1 Lecture 05:49
Types of Modelling
05:49
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Modelling Sequential and Combination Circuits
3 Lectures 19:45
Simulation And Synthesis
03:17

Assign and Always Statements
06:10

Blocking and Non-blocking Assignments
10:18
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Examples of RTL coding
1 Lecture 06:20
Illustrative Examples
06:20
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Modules
1 Lecture 12:20
Modules in detail
12:20
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Start Simulating
3 Lectures 24:46
Design and Test Bench
12:28

TB for Combination Circuit
04:22

TB for Sequential Circuit
07:56
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Summary
1 Lecture 07:18
Summary
07:18
About the Instructor
3.9 Average rating
289 Reviews
4,070 Students
6 Courses
Hardware Engineer

A post graduate in electronics engineering with 8+ years of industrial experience in ASIC design and Verification using System Verilog at major semiconductor companies. A passionate and continuous learner in emerging technologies in VSLI and also interested in other technical domains related to programming. Finds energy in learning new technologies and and sharing knowledge with others.

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