How To Implement Your First VHDL Design on FPGA
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How To Implement Your First VHDL Design on FPGA

Learn VHDL Syntax and realize a simple design on FPGA using VHDL starting from scratch
3.0 (89 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
2,895 students enrolled
Created by SURF VHDL
Last updated 7/2017
English
Price: Free
Includes:
  • 1 hour on-demand video
  • 1 Article
  • 6 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Learn a good approach on Digital Design on FPGA
  • Learn Basic VHDL Syntax
  • Start VHDL Design on FPGA
  • Simulate VHDL Design using Modelsim
  • Debug VHDL Design
  • Layout VHDL Design on FPGA
  • Configure an FPGA and test a VHDL design
View Curriculum
Requirements
  • Basic of boolean algebra
  • Basic of digital electronics
  • Desire to learn
Description

This course is not sponsored or affiliated with Udemy, Inc.

Do you like to start with VHDL without pain?

Here you can watch a complete example about how to implement your first VHDL design on FPGA.

You will learn step by step how to implement a simple VHDL design on FPGA starting from the architecture definition to the FPGA layout.

During this course, you will learn how to:

  • Define hardware architecture
  • Write the VHDL code
  • Simulate your VHDL code using ModelSim
  • Debug the VHDL code
  • Layout on FPGA
  • Test the design

You start to learn how to write a good VHDL/RTL and how to approach the FPGA world.

In the VHDL Syntax section you can learn the VHDL Syntax, all what you need to start with VHDL

Happy learning!

Surf-VHDL Team!

Who is the target audience?
  • This course is for people who love Digital Design
  • Desire to learn how to start good gesign on FPGA using VHDL
  • Want to learn VHDL an need an easy introduction to the language
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Curriculum For This Course
8 Lectures
01:05:47
+
Intro
2 Lectures 02:53

Why you should join this course. Watch what you are going to learn.

You can start from here if you already know the basic of VHDL. If you need to know the VHDL Syntax you can start from "VHDL Syntax" section and learn the basic of VHDL.

I hope you enjoy the course!

Introduction top the course
02:46

Download the eBook where you can find the 10 basic rules to implement a good VHDL Design. In the eBook you will find the guideline for the implementation of the course

The 10 steps to implement a good VHDL design on FPGA
00:07
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VHDL Course
5 Lectures 58:57

Let's start to learn good practice for digital design implementation. You can apply this methodology to all your other work

Lesson 01 - How to Start a Good VHDL Design
12:58

In this second video you will learn how to implement VHDL test bench for your design and start to simulate it using ModelSim. At the end of the video you will be able to

  • setup a VHDL test bench
  • simulate the design
  • create ModelSim simulation script
Lesson 02 - How to simulate your VHDL design using ModelSim
15:19

After VHDL Design and Simulation is the time to Layout the VHDL code on FPGA. In this video you will learn how to:

  • create a complete Quartus II project
  • Layout the VHDL code on FPGA
  • setup the pin-out
  • create Quartus II script file.

During the VHDL design test you will find a problem…

Lesson 03 - Layout and Test VHDL Design on DE0 Altera Board
12:12

Introduce the debounce logic in order to filter external spikes

Lesson 04 - Introduce de-bouncer
05:59

Layout fixed version of design and test on DE0 altera board

Lesson 05 - Simulate, Layout and Test
12:29
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BONUS
1 Lecture 03:56

When you simulate your VHDL code, sometimes you need to export your simulation result or to read the input stimuli from an external file. Let's see how we can do that.

Bonus 2 - Introduction to TextIO library
03:56
About the Instructor
SURF VHDL
4.4 Average rating
120 Reviews
3,116 Students
2 Courses
The Easiest Way to Learn VHDL

We want to support FPGA/ASIC junior and, why not, senior hardware designers in finding examples and useful hints for their VHDL designs.

Our target is to enable you to “surf” the VHDL:

We made the VHDL learning experience as simple as it can be.

We are sharing with you everything that actually helped ourselves in mastering the VHDL.

We strongly believe in knowledge sharing as one of the most important means to improve this world.

We would very much appreciate your cooperation either by submitting your questions or by sharing the link to this website with friends and colleagues

Enjoy the experience!