This course is a thorough introduction to the Verilog language. The emphasis is on writing Verilog model, both behavioral and structural source code and Register Transfer Level (RTL). This Sessions addresses targeting Xilinx FPGA devices . There is a lecture section for each main topic. This presents a basic foundation for the language. The Knowledge gained can be applied to any digital design by using a top-down or Bottom-up synthesis design approach. This course combines lectures with lab exercises to strengthen key concepts. You will also learn advanced coding techniques that will increase your overall Verilog.
The Main goal of this course is to make you familiar with developing a RTL Verilog model, both behavioral and structural, using as much of the language as possible, and writing a verification test cases and User constraints files for that model.
Who should take this course?
This course is Designed for designers who are new to Verilog and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. And Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs.
At the end of my course, students will be able to :
After the course students with little Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. and
Ø Write RTL Verilog code for synthesis
Ø Write Verilog test fixtures or Test benches for simulation
Ø Target and optimize Xilinx FPGAs by using Verilog
Ø Run a timing simulation by using Xilinx ISim libraries
Ø Create and manage designs within the Xilinx Design Suite
Ø Correctly model combinational and sequential hardware blocks
Ø Write User constraints files for any FPGA board.
What will students need to know or do before starting the course? :
Ø Basic digital design knowledge
Ø Download the Xilinx ISE Design suite 14.4 System Edition and Install In to your System.
Ø Digilent NEXYS 2 Board WITH Spartan 3E -500E or 1200 E .
This section addresses the syntax and Lexical conventions like comments , Keywords of the language .and also Number representations and main data types used while modeling.
This section describes the Operators are used in Verilog to construct the statements and conditions. Here we learn all operators used in verilog with Examples .
This section about the how to use the assignments for different modeling’s and Guide lines to write good verilog model .
Low power and low area Static Random Access Memory (SRAM) is essential for System on Chip (SoC) technology. Dual-Port (DP) SRAM greatly reduces the power consumption by full current-mode techniques for read/write operation and the area by using Single-Port (SP) cell. An 8 bit DP-SRAM is proposed in this study. Negative bit-line technique during write has been utilized for write-assist solutions. Negative voltage is generated on-chip using capacitive coupling. The proposed circuit design topology does not affect the read operation for bit interleaved architectures enabling high-speed operation. Designed in XILINX ISE 14.4 Simulation results and comparative study of the present scheme with state of-the art conventional schemes proposed .
Traffic lights are the signaling devices used to manage traffic on multi-way road. These are positioned to control the competing flow of the traffic at the road intersections to avoid collisions. By displaying lights (red, yellow and green), they alternate the way of multi-road users. The implementation of traffic Light Controller can be through a Microcontroller, Field Programmable Gate Array or Application Specific Integrated Circuit. FPGA implementation is advantageous over ASIC and microcontroller; number of IO ports and performance compared to microcontroller and implementation with FPGA is less expensive compared to ASIC design. This paper presents the FPGA implemented low cost advanced TLC system using ChipScope Pro and Virtual Input Output. The TLC implemented is one of the real and complex signaling lights in Kingdom of Bahrain, for pedestrian way included four roads and sensors and camera assisted motorway. The system has been implemented in hardware using Spartan-3E FPGA.
As a video image display interface standard, VGA interface has been widely used in the embedded system. Due to the lack of professional VGA display controller in most embedded systems, splash screen, even blank screen problems may appear while displaying the high-resolution video image. The design illustrates the implement method of VGA display controller, By using The FPGA board the design stores data that gets from the User and then reads them out in form of VGA display interface standard into D/A converter which will convert the data into analog signals to display. The whole operation above is controlled by USER by writing the code . So such a design can effectively solve the problems caused by insufficient bandwidth in the displaying, what’s more, it can reduce the pressure of the CPU. The article gives the internal detailed design of VGA, which includes generation of VGA timing signal, finite state machine and logic control, but also presents analysis of practical tests rendering. This entire code is working on the SPARTAN 3E Fpga board .
I, Hassan Uddin Shaik, having vast experience in the field of Embedded Systems and VLSI. I have 8+ Years’ experience and worked in major fields of Embedded Systems and VLSI.
Programming Languages known: Assembly, C, C++, JAVA, J2ME
Database: MS-Access, ORACLE
ScriptingLanguages: HTML, PHP
OperatingSystems: DOS, UNIX, WINDOWS, LINUX, FreeRTOS, MicroCOS-III.
HardwareKnowledge: Knowledge of hardware components, Networking and Embedded Systems.
Microcontrollers: ARMCortexM3–LPC1768, TI-LM3S89, STM32, ADE7xxx (Analog Devices), ARM7TDMI–LPC2148, MSP430x42x(Texas Instruments), AT89S51, Atmega, PIC18F, Xmega, FPGASpartan
IDE: Kiel, IAR, Atmega(AVR)studio, Mplab-x
Tools: COMSOL, L-Edit, SUPREME, CASINO, ACESSimulations, SPIP, BSIM, NGSPICE, PSPICE, MOSES1.2,
Microtek (Simulating Software), Synopsys, Cadence, SOC Encounter, Xilinx
EducationProfile: Ph.D : Pursuing at Jodhpur National University (expected to finish by January 2016); M.S-MicroNanoFabrication from DTU (Denmark Technical University-Denmark); M.Tech– Nano Electronics from VIT University (Vellore– Tamilnadu); B.Tech–Electronics and Communications from DVRCET–JNTUH.
ResearchProfile: ResearchFellow at KTH–Sweden(2 months), Research Fellow at UTO(University of Oldenberg)–Germany (2 months); Research Fellow at EPFL–Zurich (2 months); Research Fellow at JNCASR (IISC -Bangalore); Research Assistant at UUM (Universiti Utara Malaysia)
Journals: Nano bits: customizable scanning probe tips
Published in – IOP Nanotechnology