VLSI Digital Design using Verilog and hardware: Handson_temp
3.1 (29 ratings)
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VLSI Digital Design using Verilog and hardware: Handson_temp

A Complete RTL Package
3.1 (29 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
183 students enrolled
Last updated 2/2017
English
Current price: $10 Original price: $50 Discount: 80% off
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Includes:
  • 18.5 hours on-demand video
  • 5 Articles
  • 63 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • After the course students with little Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.
  • Write RTL Verilog code for synthesis
  • Write Verilog test fixtures or Test benches for simulation
  • Target and optimize Xilinx FPGAs by using Verilog
  • Run a timing simulation by using Xilinx ISim libraries
  • Create and manage designs within the Xilinx Design Suite
  • Correctly model combinational and sequential hardware blocks
  • Write User constraints files for any FPGA board.
  • Knowledge-intensive and industry-oriented program
View Curriculum
Requirements
  • Basics in any programming and part of Electronics
Description

Course Description:

This course is a thorough introduction to the Verilog language. The emphasis is on writing Verilog model, both behavioral and structural  source code  and Register Transfer Level (RTL). This Sessions addresses targeting Xilinx  FPGA devices . There is a lecture section for each main topic. This presents a basic foundation for the language. The Knowledge  gained can be applied to any digital design by using a top-down or Bottom-up synthesis design approach. This course combines  lectures with lab exercises to  strengthen key concepts. You will also learn advanced coding techniques that will increase your overall Verilog.

Objective:

The Main goal of this course is to make you familiar with developing a RTL  Verilog model, both behavioral and structural, using as much of the language as possible, and writing a verification test cases and User constraints files for that model.

Who should take this course?

This course is Designed for designers who are new to Verilog and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. And  Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs.

At the end of my course, students will be able to :

After the course  students with little Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. and

Ø  Write RTL Verilog code for synthesis

Ø  Write Verilog test fixtures or Test benches  for simulation

Ø  Target and optimize Xilinx FPGAs by using Verilog

Ø  Run a timing simulation by using Xilinx  ISim  libraries

Ø  Create and manage designs within the Xilinx Design Suite

Ø  Correctly model combinational and sequential hardware blocks

Ø  Write User constraints files for any FPGA board.

What will students need to know or do before starting the course? :

Ø  Basic digital design knowledge

Software Tools

Ø  Download the Xilinx ISE Design suite 14.4 System Edition and Install In to your System.

Hardware

Ø  Digilent  NEXYS 2 Board   WITH Spartan 3E -500E or 1200 E .

 

Who is the target audience?
  • Bachelors in Electronics with minimum programming knowledge
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Curriculum For This Course
110 Lectures
18:23:35
+
Introduction to Verilog
16 Lectures 03:21:27

Verilog Introduction : (Continuation) Design Methodology, Modules
08:31

This section addresses the syntax and Lexical conventions like comments , Keywords  of the language .and also Number representations and main  data types  used while modeling.

Preview 19:03

Verilog Introduction : (Continuation) Number Specification
14:08

Verilog Introduction : (Continuation) Data Types
07:21

This section describes the Operators are used in Verilog  to construct the statements and conditions. Here we learn  all operators used in  verilog with Examples  .

Verilog Operators: Logical Operators, Bitwise Operators
13:40

Verilog Operators: (Continuation) Reduction, Shift & Conditional Operators
19:56

Verilog Operators: (Continuation) Replecation operators and Relational Operators
09:10

Verilog Operators: (Continuation) Equality Operator, Arithamatic Operators
19:19

This section about the  how to use the assignments for different modeling’s  and Guide lines to write good verilog model .

Verilog Continuous Assignments
13:50

Verilog Procedural Assignments
11:09

Verilog Blocking and Non Blocking Assignments
14:57

Verilog : Conditional Statements (If - Else)
07:16

Verilog: Conditional Statements (Case)
06:23

Verilog : Loop Statements
13:52

Verilog : Coding Guidelines
05:24
+
Number Systems
3 Lectures 41:12
Number Systems: Definition and Radix Conversion
12:53

Number Systems: Weighted codes, Non weighted Codes
18:14

Number Systems: Gray Code, Gray Code Conversion, Error Detection Codes
10:05
+
Digital Design Combination:
40 Lectures 06:05:04
Multiplexer : Theory
07:16

Multiplexer : Program
11:35

Multiplexer: Program TestBench and simulation Results
12:01

Multiplexer : Hardware
05:24

Demultiplexer
06:11

Encoders : Theory
07:20

Encoders : Program
08:29

Encoders: Program TestBench and simulation Results
13:56

Encoder : Hardware
06:56

Priority Encoders: Theory
07:13

Priority Encoders: Program
08:33

Priority Encoders: Program TestBench and simulation Results
13:53

Priority Encoders: Hardware
09:22

Decoders : Theory (Part 1)
05:51

Decoders : Theory (Part 2)
04:35

Decoders : Program
11:45

Decoder Program : TestBench and simulation Results
11:16

Decoders : Hardware
03:36

Comparators : Theory
05:43

Comparators : 2 Bit Program
12:24

Comparators 2bit Program TestBench and Simulation Results
18:21

Comparators : 2 Bit Hardware
08:52

Comparators : nbits Program
15:39

Majority Gate: Program
10:20

Majority gate Program TestBench and Simulation Results
12:33

Majority Gate: Hardware
03:15

Arithmatic Circuits: Half Adder Theory
07:13

Arithmatic Circuits: Full Adder Theory
10:31

Arithmatic Circuits: Ripple Carry Adder Theory
05:16

Arithmatic Circuits: Ripple Carry Adder Program
18:57

Arithmatic Circuits: Ripple Carry adder Program TestBench and Simulation Result
12:44

Arithmatic Circuits: Ripple Carry Adder Hardware
04:58

Arithmatic Circuits: Universal Ripple Carry Adder Theory
06:18

Code Converters : bin to bcd program
09:51

Code Converters: bin to bcd program TestBench and simulation Results
16:17

Code Converters : bin to bcd Hardware
04:25

Code Converters : bin to gray program
09:19

Code Converters : bin to gray program TestBench and simulation Results
12:11

Code Converters : bin to gray Hardware
04:00

Combinational circuits assignments
00:45
+
Digital Design Sequential:
30 Lectures 04:33:32
Sequentail Circuits: Theory
06:00

Flip Flops & Latches: SR Flip Flop Theory
16:32

Flip Flops & Latches: SR Flip Flop Program
11:08

Flip flops & Latchs : SR FlipFlop Program TestBench and simulation Results
16:54

Flip Flops & Latches: SR Flip Flop Hardware
04:20

Flip Flops & Latches: JK Flip Flop Theory
10:05

Flip Flops & Latches: D Flip Flop Theory
08:39

Flip Flops & Latches: D Flip Flop Program
18:13

Flip Flops & Latches: D Flip Flop Hardware
02:24

Registers : Theory
12:34

Registers: SISO Theory
12:58

Registers : SISO Program
13:48

Registers: SISO program TestBench and simulation Results
14:30

Registers : SISO Hardware
02:03

Registers : SIPO Theory
07:52

Registers : SIPO Program
08:58

Registers : SIPO program TestBench and simulation Results
11:41

Registers : SIPO Hardware
01:37

Registers : PIPO Theory
05:04

Registers : PIPO Program
11:51

Registers : PIPO program TestBench and simulation Results
14:19

Registers : PIPO Hardware
03:15

Counters: Jhonson Counter Theory
05:32

Counters: Jhonson Counter Program
08:09

Counters : Jhonson counter program TestBench and simulation Results
12:17

Counters: Jhonson Counter Hardware
01:59

Counters: RING Counter Theory
08:00

Counters: RING Counter Program
08:33

Counters : Ring Counter Program TestBench and simulation Results
12:18

Counters: RING Counter Hardware
01:59
+
Projects
15 Lectures 02:33:24

Low power and low area Static Random Access Memory (SRAM) is essential for System on Chip (SoC) technology. Dual-Port (DP) SRAM greatly reduces the power consumption by full current-mode techniques for read/write operation and the area by using Single-Port (SP) cell. An 8 bit DP-SRAM is proposed in this study. Negative bit-line technique during write has been utilized for write-assist solutions. Negative voltage is generated on-chip using capacitive coupling. The proposed circuit design topology does not affect the read operation for bit interleaved architectures enabling high-speed operation. Designed in XILINX ISE 14.4 Simulation results and comparative study of the present scheme with state of-the art conventional schemes proposed .

Design of SRAM in Verilog
00:27

Design of SRAM in Verilog : Program
17:14

Design of SRAM in Verilog : Program TestBench and Simulation
06:34

Traffic lights are the signaling devices used to manage traffic on multi-way road. These are positioned to control the competing flow of the traffic at the road intersections to avoid collisions. By displaying lights (red, yellow and green), they alternate the way of multi-road users. The implementation of traffic Light Controller can be through a Microcontroller, Field Programmable Gate Array or Application Specific Integrated Circuit. FPGA implementation is advantageous over ASIC and microcontroller; number of IO ports and performance compared to microcontroller and implementation with FPGA is less expensive compared to ASIC design. This paper presents the FPGA implemented low cost advanced TLC system using ChipScope Pro and Virtual Input Output. The TLC implemented is one of the real and complex signaling lights in Kingdom of Bahrain, for pedestrian way included four roads and sensors and camera assisted motorway. The system has been implemented in hardware using  Spartan-3E FPGA.

FPGA Implementation of an Traffic Light Controller using Verilog HDL
00:37

FPGA Implementation of Traffic Light: Program
19:45

FPGA Implementation of Traffic Light : Program TestBench and Simulation
19:44

FPGA Implementation of Traffic Light : Hardware
01:21

As a video image display interface standard, VGA interface has been widely used in the embedded system. Due to the lack of professional VGA display controller in most embedded systems, splash screen, even blank screen problems may appear while displaying the high-resolution video image. The design illustrates the implement method of VGA display controller, By using The FPGA board the design stores data that gets from the User  and then reads them out in form of VGA display interface standard into D/A converter which will convert the data into analog signals to display. The whole operation above is controlled by USER by writing the code . So such a design can effectively solve the problems caused by insufficient bandwidth in the displaying, what’s more, it can reduce the pressure of the CPU. The article gives the internal detailed design of VGA, which includes generation of VGA timing signal, finite state machine and logic control, but also presents analysis of practical tests rendering. This entire code is working on the SPARTAN 3E  Fpga board .

DESIGN OF VGA DISPLAY SYSTEM BY USING FPGA
00:43

Design of VGA Display System using FPGA: Program (1)
17:57

Design of VGA Display System using FPGA: Program (2)
19:16

Design of VGA Display System using FPGA: Program TestBench and Simulation(1)
18:00

Design of VGA Display System using FPGA: Program TestBench and Simulation(2)
09:28

Design of VGA Display System using FPGA: Hardware
05:19

Verilog Programming On BASYS-3 with VIVADO.
13:53

Verilog Programming On BASYS-3 with VIVADO_hardware
03:05
About the Instructor
Hassan Uddin Shaik
3.1 Average rating
29 Reviews
195 Students
3 Courses
Learn from the LEADER

I, Hassan Uddin Shaik, having vast experience in the field of Embedded Systems and VLSI. I have 8+ Years’ experience and worked in major fields of Embedded Systems and VLSI.

Programming Languages known: Assembly, C, C++, JAVA, J2ME

Database: MS-Access, ORACLE

ScriptingLanguages: HTML, PHP

OperatingSystems: DOS, UNIX, WINDOWS, LINUX, FreeRTOS, MicroCOS-III.

HardwareKnowledge: Knowledge of hardware components, Networking and Embedded Systems.

Microcontrollers: ARMCortexM3–LPC1768, TI-LM3S89, STM32, ADE7xxx (Analog Devices), ARM7TDMI–LPC2148, MSP430x42x(Texas Instruments), AT89S51, Atmega, PIC18F, Xmega, FPGASpartan

IDE: Kiel, IAR, Atmega(AVR)studio, Mplab-x

Tools: COMSOL, L-Edit, SUPREME, CASINO, ACESSimulations, SPIP, BSIM, NGSPICE, PSPICE, MOSES1.2,

Microtek (Simulating Software), Synopsys, Cadence, SOC Encounter, Xilinx

EducationProfile: Ph.D : Pursuing at Jodhpur National University (expected to finish by January 2016); M.S-MicroNanoFabrication from DTU (Denmark Technical University-Denmark); M.Tech– Nano Electronics from VIT University (Vellore– Tamilnadu); B.Tech–Electronics and Communications from DVRCET–JNTUH.

ResearchProfile: ResearchFellow at KTH–Sweden(2 months), Research Fellow at UTO(University of Oldenberg)–Germany (2 months); Research Fellow at EPFL–Zurich (2 months); Research Fellow at JNCASR (IISC -Bangalore); Research Assistant at UUM (Universiti Utara Malaysia)

Journals: Nano bits: customizable scanning probe tips

Published in – IOP Nanotechnology