FPGA Design with High Level Synthesis Tool (VIVADO HLS)
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FPGA Design with High Level Synthesis Tool (VIVADO HLS)

Design,Simulate,Synthesize and Export IP with VIVADO HLS (High Level Synthesis) : An FPGA Design Approach with C/C++
0.0 (0 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
4 students enrolled
Created by Krishna Gaihre
Last updated 7/2017
English
Current price: $10 Original price: $100 Discount: 90% off
5 hours left at this price!
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Includes:
  • 2 hours on-demand video
  • 2 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • FPGA Design with High Level Synthesis Design Flow :Programming with C/C++
  • Writing C/C++ Project on High Level Synthesis (VIVADO HLS)
  • Designing, Simulating, Synthesizing and Exporting HLS Project
  • Creating IP from HLS methodology , Importing it on VIVADO IPI & interfacing with Zynq Processing System
  • Design, Synthesize, Simulate: Counter, Matrix Multiplier, Frequency Modulator and Numerically Controlled Oscillator and Exporting Design to VIVADO IP Integrator
  • Debugging and Optimizing HLS Project for Resource Utilization on Targeted ZedBoard FPGA
  • Image Processing with VIVADO HLS: Utilizing Computer Vision & Image/Video Processing Libraries on HLS
View Curriculum
Requirements
  • Basic Idea of C, C++
  • Basic Idea of HDL (VHDL/Verilog)
  • FPGA Design Flow
  • Basic Idea of VIVADO Design Environment
Description

High Level Synthesis is new approach on FPGA Design with C/C++ Language.This Course covers "How to Install VIVADO along with HLS,  Creating new project on HLS, Running C Simulation on HLS, Synthesizing the HLS Project's which converts C/C++ Source in to Verilog/VHDL and System C, Running C/RTL Co-simulation, Implementing HLS Design in to IP core Format or Exporting HLS Design to VIVADO IPI.

After Completing this course you will be able to Design, Simulate,Synthesize and Implement/Export HLS projects. HLS includes large number of C/C++ Libraries for Computer Vision (OpenCV), Video/Image Processing and Mathematical Computations which is very much complex while implementing on HDL/RTL. So HLS is flexible and easy way for implementing such AI and Math Algorithm on FPGA.

In this Lab you are going to do lab on Design, Simulation , Synthesis and Implementation (Export Design) of Counter, Matrix Multiplier, Frequency Modulator, Numerically Controlled Oscillator (NCO Design) in C++. You will also integrate the exported HLS project with Zynq Processing System at VIVADO IP Integrator and Synthesize, Implement the Project on VIVADO IPI.

Who is the target audience?
  • Electrical and Electronic Engineering
  • FPGA Design Enthusiast
  • Computer Science
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Curriculum For This Course
9 Lectures
02:09:42
+
Section 2 Design , Simulation,Synthesizing and Implementing with VIVADO HLS
6 Lectures 01:25:19
Lab 21 Matrix Multiplier Design and Simulation on HLS: Theoretical Overview
05:52

Section 2 Lab 21 Design of Matrix Multiplier on VIVADO HLS
19:54

Section 2 Lab 22 Frequency Modulator Design Overview
13:21

Section 2 Lab 22 Frequency Modulator Design Simulation and Synthesizing on HLS
15:12

Section 2 Lab 23 NCO Design Simulation and Synthesizing Overview
11:04

Section 2 Lab 23 NCO Lab on VIVADO HLS and IPI
19:56
About the Instructor
Krishna Gaihre
4.2 Average rating
7 Reviews
103 Students
4 Courses
FPGA Design Engineer with Expertise on Embedded Design

Krishna is an FPGA Engineer and Research Lead at Digitronix Nepal. Krishna had graduated on M.Sc Engineering Degree after B.E in Electronics and Communication Engineering.He has several paper published on IEEE and Google Scholar and he also have requested for Patent for Image Processing IP on FPGA.He is working on FPGA , ASIC and VLSI design and Verification from past 5+ years.He has worked for different multinational companies for FPGA/ASIC/VLSI Design and Verification.There are different IP and Bus verification Digitronix Nepal has marked for Industries.He had worked with different application based projects as Signal Processing for ADAS, IIOT and Computer Vision Applications. He had expertise on FPGA Design with VHDL/Verilog and Tcl with Tools experience of Xilinx ISE, VIVADO and Modelsim. Krishna had worked with Xilinx 7 Series FPGA boards and Ultrascale Boards for different embedded and custom applications.