Mastering Xilinx DSP IP Cores: FIR, CIC, DDS, FFT

Name: Mastering Xilinx DSP IP Cores: FIR, CIC, DDS, FFT
Rating: 4.0 (15 reviews)

Practical FPGA DSP with Xilinx IP cores (FIR, CIC, DDS, FFT): from simulation to real-time deployment on Zynq 7000

Created byAleksei Rostov

Last updated 3/2025

English

English [Auto],

What you'll learn

How to Simulate Xilinx DSP IP cores (FIR, CIC, DDS compiler and FFT) in Vivado with Verilog testbenches & Python analysis
How to Integrate IP cores into FPGA designs on development board
How to Develop standalone embedded C application to interface with DSP IP cores
How to Automate Vivado & Vitis workflow with TCL and Python scripts

Course content

3 sections • 10 lectures • 2h 17m total length

Introduction1:56
Explore digital signal processing on FPGA and SoC, including real-time filtering, waveform generation, and fast Fourier transform, and learn to configure Xilinx DSP IP cores with Vivado.
Requirements and Workflow Automation8:14
Automate three workflows for Xilinx DSP IP cores: simulation with Vivado, design with Vivado, and embedded application with Vitess, using Python, NumPy, and Matplotlib.

Vivado Simulation: FIR compiler v7.221:46
Simulate four fir compiler instances in vivado using a verilog testbench and integrated AXI stream data paths with packet framing to analyze bandpass and hilbert transformations, decimator and interpolator chains.
Vivado Simulation: CIC compiler v4.010:02
simulate the CIC compiler in Vivado using a Python workflow to build the project, run the testbench, and inspect decimator and interpolator results with 16-bit data at 100 MHz.
Vivado Simulation: DDS compiler v6.09:00
Explore how to simulate the DDS compiler v6.0 in Vivado, featuring two IP core instances with included and external phase generators, phase increment control, and chirp signal testbenches.
Vivado Simulation: Fast Fourier Transform v9.18:02
Configure and simulate the Xilinx F50 IP core in Vivado 2024, implementing forward and inverse FFT, with a Verilog testbench, runtime-selectable transform length, and Python plots.

Zynq 7000 SoC: development C application to interface with FIR compiler IP cores24:58
Shows configuring a Zynq 7000 SoC in Vivado Invitus 2024, building Vitus project to run four fir compiler IP cores, and interfacing with a C embedded application via AXI domain.
Zynq 7000 SoC: development C application to interface with CIC compiler IP cores20:34
Develop a C embedded application on Zynq 7000 SoC to interface with two key compiler IP cores, decimator and interpolator, via Vitus workflow and AXI stream switches.
Zynq 7000 SoC: development C application to interface with DDS compiler IP cores15:57
Interface two DS compiler IP cores on a Zynq 7000 SoC with a development C application, enabling exit-domain data transfer and AXI-Stream communication using phase generator and lookup table.
Zynq 7000 SoC: development C application to interface with FFT IP core17:26
Implement an embedded C application to interface the Xilinx FFT IP core on a Zynq 7000 SoC, using AXI streams, a shared port, and a subset converter for runtime configuration.

Requirements

Vivado 2024.2
Vitis 2024.2
Python >= 3.0
Powershell
Any development board with Zynq 7000 SoC (Arty z7-20 as example)

Description

Whether you're a beginner or an engineer looking to level up your FPGA skills, this course will guide you step by step through the entire workflow—from simulation to real-world deployment on the Arty Z7-20 development board.

This hands-on course covers four essential Xilinx DSP IP cores: FIR Compiler, CIC Compiler, DDS Compiler, and Fast Fourier Transform (FFT). You’ll learn how to configure and simulate each core using Vivado 2024.2, generate Verilog testbenches, and analyze the outputs using Python.

We’ll explore multiple configurations for each IP core:

FIR Compiler as a bandpass filter, Hilbert transformer, interpolator, and decimator
CIC Compiler as both an interpolator and decimator
DDS Compiler in two configurations: with phase generator (internally generated phase increment) and without phase generator (streaming external phase input)
FFT IP Core for both forward and inverse (backward) transforms

Next, we take everything to the hardware. You’ll integrate these cores into practical FPGA designs and deploy them on a Zynq-7000 SoC. We'll develop bare-metal C applications in Vitis to manage data transfer between the processing system (PS) and programmable logic (PL) using AXI DMA.

You’ll also learn how to automate your development workflow with TCL scripts for Vivado and Vitis, and how to debug FPGA designs using System ILA.

By the end of this course, you’ll have a comprehensive, hands-on understanding of DSP design with Xilinx IP cores—both in simulation and on real hardware.

This course is ideal for FPGA beginners, digital designers, embedded engineers, and anyone working with signal processing systems on Xilinx platforms.

Who this course is for:

Beginner
Intermediate

Mastering Xilinx DSP IP Cores: FIR, CIC, DDS, FFT

What you'll learn

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Course content

Introduction2 lectures • 10min

Xilinx DSP IP cores simulation4 lectures • 49min

Development C application to interface with Xilinx DSP IP cores on Zynq 70004 lectures • 1hr 19min

Requirements

Description

Who this course is for: