VSD - Timing ECO (engineering change order) webinar
What you'll learn
- Design better chips
- Analyze designs, from power, performance and area perspective, altogether
- You should have completed STA-1, STA-2 and Physical Design course atleast 50%
- You should understand basic timing analogies like setup time and hold time
First, let’s define better? Better in terms of Power. Performance and Area
Every VLSI engineer, an RTL architect, or Lead Synthesis Engineer, or Senior Physical Designer, or Director of Signoff timing analysis – practically everyone is doing timing ECO at every step of their flow. I, being a part of Signoff timing analysis and Physical Design world, am doing ECO almost every day, and so I understood that its more than adding buffer and up-sizing/downsizing cells.
All of the factors or ways shown in above image impacts either dynamic power or short-circuit power or leakage power. The question is, do you know why do we still do it? Do you know how can we still do with minimally impact on other parameters? Yes, No, Don’t Know….
It’s time to unveil more than 9 strategies to do timing ECO and below are few of them
- Routing congestion aware timing ECO
- Path based analysis ECO for selected endpoints
- Replicated modules based timing ECO
- Legalized timing ECO
- Margin based timing ECO
…..and many more…
See, I told you, timing ECO is more than just adding buffers and sizing cells…Do you want to know all the strategies?
Do you want to be a better timing engineer? Engineering includes tons of changes and modifications from inception to final product. Hence its called Engineering Change Order (ECO)
Welcome all of you to my "Timing ECO webinar", which was conducted along with ~50people on 6th Jan, 2018. Join and re-live the webinar.
Who this course is for:
- Anyone who wants to understand timing ECO strategies and how it impacts overall chip PPA (power, performance, area)
- Anyone who wants to be called as "Signoff Timing Expert", rather than, "Signoff Timing Engineer"
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.
Hands on with Technology @
1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.
2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.
3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer
4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.
5) “IR aware STA” and “Low power STA”
6) Analyzed STA engine behavior for design size up to 850 million instance count ACADEMIC
1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.
2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software
1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”
2) Concurrent + Distributed MMMC STA for 'N' views
3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit
4) Placement-aware ECO Methodology - No Slacking on Slack
Tips on order in which you need to learn VLSI and become a CHAMPION:
If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.
Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively
Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.
And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course
All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle
Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor
Connect with me for more guidance !!
Hope you enjoy the session best of luck for future