VSD - SoC Design of the PicoRV32 RISCV micro-processor
4.4 (31 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
296 students enrolled

VSD - SoC Design of the PicoRV32 RISCV micro-processor

Freedom to build micro-processors
4.4 (31 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
296 students enrolled
Last updated 6/2018
English
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Current price: $135.99 Original price: $194.99 Discount: 30% off
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This course includes
  • 4 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Run a full physical design flow from RTL design to GDSII, making it ready for tape-out.
  • For freshers, this course will make them industry ready and might increase their chances of getting placed or work for tier-1 company. Assignment submission is a must
Requirements
  • Knowledge about previous course "VSD - Making the Raven chip: How to design a RISC-V SoC" is nice to have, but not must to have as this course focuses on Physical design concepts, like synthesis, placement, routing, DRC, LVS and tapeout needs
  • Knowledge about clock tree synthesis/STA/custom layout is nice to have and can be taken from existing VSD courses Udemy. Take up the courses "VSD - clock tree synthesis", "VSD - Static timing analysis" and "VSD - Custom Layout" on Udemy
Description

This webinar was conducted on 2nd June 2018

After successful webinar on Making of Raven Chip, this time we take the chip forward and implement using end-to-end opensource EDA tools, and all on efabless cloud. What does this mean to us? It means, you can start innovating on a design, build RTL and do synth/PD/LVS/DRC all using opensource EDA framework and not pay a single penny for license.

The big question How is this possible? Thereby, I welcome you all to my next (follow-up) webinar with Tim Edwards and Mohamed Kassem

About instructors -

Tim Edwards

Tim Edwards has been doing analog VLSI design and collecting and developing open-source EDA tools for over 25 years.  He has worked for the Johns Hopkins Applied Physics Lab, startups MultiGiG (bought by Analog Devices) and most recently, eFabless

Mohamed Kassem

Mohamed Kassem is the cofounder and CTO of eFabless corporation. Prior to launching eFabless in 2014, Mohamed held several technical and global leadership positions within TI's Wireless Business Unit. He joined TI in 2000 at the beginning of the digital telephony revolution fueled by the unprecedented integration of major phone functions on a single SoC. He led the first development of 45nm, 28nm analog & mixed-signal IP functions for wireless applications processors. Mohamed holds a masters degree in electrical engineering from the University of Waterloo, Ontario, Canada.


Who this course is for:
  • Anyone curious to know end-to-end aspects of chip designing i.e from SOC design to tapeout, which involves lot of steps like placement, routing, clock tree synthesis, DRC cleanup, LVS fixing
  • Anyone curious to know how to achieve all of above using all EDA open-source tools. Not a single penny to be paid as license fee
  • Anyone who wishes to innovate, implement and submit a paper on any design, implemented using open-source tools
Course content
Expand all 28 lectures 04:06:22
+ efabless interactive tutorial
3 lectures 27:48
Introduction to efabless platform and webinar agenda
09:14
LIVE QnA with participants and steps to login to efabless marketplace
09:35
+ CloudV interactive tutorial
3 lectures 28:56
Introduction to CloudV application
10:02
Steps to synthesize to target process and export to open-galaxy
09:30
Steps to import synthesized netlist into open-galaxy
09:24
+ Synthesis flow interactive tutorial
5 lectures 48:38
Steps to start synthesis flow tool and run synthesis
09:56
Pin arrangement UI and automatic grouping of vectors
10:09
Few tips on pin-placement and floor-planning chip
10:02
LIVE QnA with participants regarding pacement and STA
08:44
Routing post-route STA and LVS check
09:47
+ LVS & DRC
4 lectures 38:13
Steps to fix LVS, Magic short-cut keys and run DRC
09:58
LIVE QnA with participants on LVS and steps to fix DRC
09:06
DRC cleaning steps LIVE and QnA with partcipants on DRC
10:36
LIVE QnA with participants about future of qflow and efabless
08:33
+ Full chip integration in open-galaxy
4 lectures 34:45
Steps to create a new project for floorplanning and integration
07:45
Steps to populate layout from library manager and select SPI block
08:10
Steps to select, generate copies and arrange pad frames
09:42
Steps to abut pads and ensure pad-frame is DRC clean
09:08
+ Signal routing
5 lectures 47:53
'reset' signal routing steps
10:12
sck, csb, other signal routing and DRC clean step
10:13
Dynamic power estimation and power routing
09:42
Tie-down unused inputs, add substrate contacts and antenna diodes
09:26
Add pin labels, review completed layout and final LVS check
08:20
+ Challenge & Conclusion
2 lectures 06:34
Challenge description and mode of submission
04:55
Conclusion
01:39