VSD - RISCV : Instruction Set Architecture (ISA) - Part 1b
What you'll learn
- Understand RISC-V architecture in greater detail, and, as per speculations, this is the architecture which you will find in almost 1 trillion mobile devices
- Learn how computers and processors does basic calculations
- This course will help understand why RISC-V is the next big thing
- This course lays the foundation to do RISC-V software basic labs
- You should have completed RISC-V ISA Part 1a online course
- You should be familiar with boolean addition and subtraction concepts
- You should be familiar with number systems
**pre-launch with 5 videos**
This course is in continuation with my previous course "VSD - RISCV : Instruction Set Architecture (ISA) - Part 1a" which dealt with RV64I integer instructions. We also looked at a sample program coded in RISC-V assembly language and viewed the contents of all 32 registers present in RISC-V architecture.
All concepts viewed in Part 1a form the basis of this course and viewer is expected to cover Part 1a course atleast 70%. This course deals with some advanced topics of multiply extension (RV64M) and floating point extension (RV64FD) of the RISC-V architecture - An important one needed in today's fast changing computing world.
We also have explored some facts about hardware, which is the basis of next course (to be launched soon) where we will code the RISC-V ISA using verilog.
So let's get started - again....Happy Learning
I would like to Thank SiFive, a company that was founded by the creators of RISC-V ISA.
I would also like to Thank Prof. David Patterson and his book "Computer Organization And Design - RISCV edition" which immensely helped in the making of this course.
Let's get inside computers...
Who this course is for:
- Anyone who wants to learn world's first Open-Source instruction set architecture RISC-V
- Anyone who wants to learn how to write specifications for RTL coding
- Anyone looking forward to implement their own processor using all open-source tools
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.
Hands on with Technology @
1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.
2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.
3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer
4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.
5) “IR aware STA” and “Low power STA”
6) Analyzed STA engine behavior for design size up to 850 million instance count ACADEMIC
1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.
2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software
1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”
2) Concurrent + Distributed MMMC STA for 'N' views
3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit
4) Placement-aware ECO Methodology - No Slacking on Slack
Tips on order in which you need to learn VLSI and become a CHAMPION:
If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.
Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively
Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.
And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course
All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle
Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor
Connect with me for more guidance !!
Hope you enjoy the session best of luck for future