VSD Intern - DAC IP design using Sky130 PDKs - Part 3
What you'll learn
- Analog VLSI Layout using MAGIC and Sky130 PDKs
- DAC IP layout design fundamentals
- VSD - DAC IP design using Sky130 PDKs - Part 1 & 2
- VSD - Custom Layout
- VSD - Circuit Design and SPICE simulations
The webinar aims to do analog layout design of a 10-bit potentiometric Digital to Analog Converter, from scratch, using Magic and Sky130 PDKs. The target is to layout and generate GDS for 10-bit potentiometric DAC with 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference. This is a follow-up webinar of "VSD Intern - DAC IP design using Sky130 PDKs - Part 2" conducted by Harshitha Basavaraju
In real world, most of the data available is in the form of analog in nature. We have two types of converters analog to digital converter and digital to analog converter. These two converting interfaces are essential to obtain the required operations of a processor to manipulate the data of digital electronic equipment and an analog electric equipment. Digital to Analog Converter (DAC) is a device that transforms digital data into an analog signal in order to interact with the real world. The digital signal is represented with a binary code, which is a combination of bits 0’s and 1’s. The digital data can be produced from a microprocessor, Field Programmable Gate Array (FPGA), or Application Specified Integrated Circuit (ASIC). There are two commonly used DAC conversions – Weighed resistors method and R-2R ladder network method. Applications of a DAC: audio amplifier, video encoder, display electronics, data acquisition systems, calibration, Digital potentiometer.
This webinar will cover:
Introduction to DAC fundamentals
Introduction to DAC IP Specifications
DAC IP design basics and tool installation
DAC Circuit Topology
Basics of DAC IP Layout
CMOS Cross Sectional View
Resistor and Capacitor Layout Theory
Magic tool Basics
Resistor Layout demo
Inverter and switch layout LIVE Labs
Inverter layout starting
Inverter Layout Continued
Inverter Layout Complete
Switch Layout starting
Switch Layout Complete
10-bit DAC layout design and post-layout analysis
2Bit DAC to 10Bit DAC starting
2Bit DAC to 10Bit DAC Complete
Output Response Evaluation
DNL and INL theory
DNL and INL Calculations
Who this course is for:
- Beginner or fresher looking to start career in analog VLSI design
- Professional Physical Design engineers looking to know more about IP design or IP blocks which they use as black box
Tips on order in which you need to learn VLSI and become a CHAMPION:
If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.
Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively
Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.
And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course
All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle
Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor
Connect with me for more guidance !!
Hope you enjoy the session best of luck for future
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.
Hands on with Technology @
1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.
2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.
3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer
4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.
5) “IR aware STA” and “Low power STA”
6) Analyzed STA engine behavior for design size up to 850 million instance count ACADEMIC
1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.
2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software
1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”
2) Concurrent + Distributed MMMC STA for 'N' views
3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit
4) Placement-aware ECO Methodology - No Slacking on Slack
I have a Master's Degree in Computer Engineering from University of Massachusetts Lowell. I have a good understanding of CMOS technology, Analog and Digital Electronics, RTL2GDS and Physical Design. I have hands-on experience of working with 65nm and SKY130nm technology. I have experience in full custom layout design of Data converters.