VSD - Functional Verification Using Embedded-UVM - Part 2
0.0 (0 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
18 students enrolled

VSD - Functional Verification Using Embedded-UVM - Part 2

Introduction to object-oriented programming
0.0 (0 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
18 students enrolled
Last updated 4/2020
English
English [Auto]
Current price: $69.99 Original price: $99.99 Discount: 30% off
5 hours left at this price!
30-Day Money-Back Guarantee
This course includes
  • 1.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
Training 5 or more people?

Get your team access to 4,000+ top Udemy courses anytime, anywhere.

Try Udemy for Business
What you'll learn
  • SoC design flow, role of Functional Verification
  • Logic Modeling, Introduction to Verilog
  • Concept of Hierarchy, Simulation-Time, and Concurrency in Hardware Modeling
  • Simulation Technology, Discrete Event Simulation
  • Verification Trends and Challenges
  • Concepts and Principles of Functional Verification
  • Testbench Architecture and Components
  • Lab – Tool Setup and Usage -- a simple DUT with traditional Verilog testbench will be provided with a Makefile to compile and simulate – Debug using waveforms
Requirements
  • Should be good with digital electronics
  • Should be good with Linux/UNIX basic commands
  • IMP - Should have completed "VSD - Functional Verification Using Embedded-UVM - Part 1" 100%
Description

Another course, "hand-crafted" for anyone and everyone, who want to move from back-end to front-end OR for people just curious to know and learn, what exactly happens in field of VLSI verification. The reason its "hand-crafted" is because it starts from very basics and in coming parts of this course, things will slowly move towards advanced level UVM.

Another reason for this course to be "hand-crafted" is due to the open-source tool used to cover labs introduced in this course. This is Part - 2 in the "Verification Series" and focused on Object-Oriented Programming

About Embedded-UVM:

Embedded UVM is an opensource implementation of IEEE 1800.2 standard of Universal Verification Methodology. In this webinar, we take a dive into Embedded UVM and its use cases as a platform for Functional Verification and SoC-FPGA based Emulation.

About Speaker:

Puneet Goel is a 1994 graduate in Electronics from Punjab Engineering College. He has 24 years of experience in the VLSI industry where he worked for STMicro, Motorola, Texas Instruments and TranSwitch. For the past 8 years, he has been working for Coverify Systems Technology, where he provides verification services and works on creating viable opensource solutions for chip verification. Puneet is the main developer of Embedded UVM.

Who this course is for:
  • Beginner electronics student, curious to know about verification
  • Professional from a different back-ground of VLSI, but wants to learn VLSI verification methodologies
  • Anybody looking to change domain to Verification from other VLSI domains
Course content
Expand all 9 lectures 01:24:20
+ Introduction
5 lectures 44:55
Introduction to object-oriented programming using class
08:10
Why A "class" is a contract - Public and Private parts of "class"
09:59
More information about public and private parts of C++ "class"
08:11
+ Fundamentals of Object Oriented Programming
4 lectures 39:25
Single responsibility principle and open closed principle
09:51
Class inheritance in C++
09:49
How Open-Closed Principle (OCP) helps tackle rigidity
09:17
Solve rigidity using inheritance and virtual functions
10:28