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- SoC design flow, role of Functional Verification
- Logic Modeling, Introduction to Verilog
- Concept of Hierarchy, Simulation-Time, and Concurrency in Hardware Modeling
- Simulation Technology, Discrete Event Simulation
- Verification Trends and Challenges
- Concepts and Principles of Functional Verification
- Testbench Architecture and Components
- Lab – Tool Setup and Usage -- a simple DUT with traditional Verilog testbench will be provided with a Makefile to compile and simulate – Debug using waveforms
- Should be good with digital electronics
- Should be good with Linux/UNIX basic commands
- IMP - Should have completed "VSD - Functional Verification Using Embedded-UVM - Part 1" 100%
Another course, "hand-crafted" for anyone and everyone, who want to move from back-end to front-end OR for people just curious to know and learn, what exactly happens in field of VLSI verification. The reason its "hand-crafted" is because it starts from very basics and in coming parts of this course, things will slowly move towards advanced level UVM.
Another reason for this course to be "hand-crafted" is due to the open-source tool used to cover labs introduced in this course. This is Part - 2 in the "Verification Series" and focused on Object-Oriented Programming
Embedded UVM is an opensource implementation of IEEE 1800.2 standard of Universal Verification Methodology. In this webinar, we take a dive into Embedded UVM and its use cases as a platform for Functional Verification and SoC-FPGA based Emulation.
Puneet Goel is a 1994 graduate in Electronics from Punjab Engineering College. He has 24 years of experience in the VLSI industry where he worked for STMicro, Motorola, Texas Instruments and TranSwitch. For the past 8 years, he has been working for Coverify Systems Technology, where he provides verification services and works on creating viable opensource solutions for chip verification. Puneet is the main developer of Embedded UVM.
- Beginner electronics student, curious to know about verification
- Professional from a different back-ground of VLSI, but wants to learn VLSI verification methodologies
- Anybody looking to change domain to Verification from other VLSI domains