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IT & SoftwareOther IT & SoftwareVLSI

VSD - Functional Verification Using Embedded-UVM - Part 2

Introduction to object-oriented programming
Rating: 0.0 out of 50.0 (0 ratings)
60 students
Created by Kunal Ghosh, Puneet Goel
Last updated 4/2020
English
English [Auto]

What you'll learn

  • SoC design flow, role of Functional Verification
  • Logic Modeling, Introduction to Verilog
  • Concept of Hierarchy, Simulation-Time, and Concurrency in Hardware Modeling
  • Simulation Technology, Discrete Event Simulation
  • Verification Trends and Challenges
  • Concepts and Principles of Functional Verification
  • Testbench Architecture and Components
  • Lab – Tool Setup and Usage -- a simple DUT with traditional Verilog testbench will be provided with a Makefile to compile and simulate – Debug using waveforms

Requirements

  • Should be good with digital electronics
  • Should be good with Linux/UNIX basic commands
  • IMP - Should have completed "VSD - Functional Verification Using Embedded-UVM - Part 1" 100%

Description

Another course, "hand-crafted" for anyone and everyone, who want to move from back-end to front-end OR for people just curious to know and learn, what exactly happens in field of VLSI verification. The reason its "hand-crafted" is because it starts from very basics and in coming parts of this course, things will slowly move towards advanced level UVM.

Another reason for this course to be "hand-crafted" is due to the open-source tool used to cover labs introduced in this course. This is Part - 2 in the "Verification Series" and focused on Object-Oriented Programming

About Embedded-UVM:

Embedded UVM is an opensource implementation of IEEE 1800.2 standard of Universal Verification Methodology. In this webinar, we take a dive into Embedded UVM and its use cases as a platform for Functional Verification and SoC-FPGA based Emulation.

About Speaker:

Puneet Goel is a 1994 graduate in Electronics from Punjab Engineering College. He has 24 years of experience in the VLSI industry where he worked for STMicro, Motorola, Texas Instruments and TranSwitch. For the past 8 years, he has been working for Coverify Systems Technology, where he provides verification services and works on creating viable opensource solutions for chip verification. Puneet is the main developer of Embedded UVM.

Who this course is for:

  • Beginner electronics student, curious to know about verification
  • Professional from a different back-ground of VLSI, but wants to learn VLSI verification methodologies
  • Anybody looking to change domain to Verification from other VLSI domains

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)
Kunal Ghosh
  • 4.2 Instructor Rating
  • 11,557 Reviews
  • 40,286 Students
  • 41 Courses

Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.

Hands on with Technology @    

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.   

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.   

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer   

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.   

5) “IR aware STA” and “Low power STA”   

6) Analyzed STA engine behavior for design size up to 850 million instance count   ACADEMIC    

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.    

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software  

PUBLICATION   

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”  

2) Concurrent + Distributed MMMC STA for 'N' views  

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit  

4) Placement-aware ECO Methodology - No Slacking on Slack  


Tips on order in which you need to learn VLSI and become a CHAMPION:

If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.

Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2  and Timing ECO webinar courses, respectively

Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.

And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course

All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle

Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor 

Connect with me for more guidance !!   

Hope you enjoy the session best of luck for future

Puneet Goel
CTO at Coverify
Puneet Goel
  • 3.9 Instructor Rating
  • 28 Reviews
  • 249 Students
  • 3 Courses

Puneet Goel is a 1994 graduate in Electronics from Punjab Engineering College. He has 24 years of experience in the VLSI industry where he worked for STMicro, Motorola, Texas Instruments and TranSwitch. For the past 8 years, he has been working for Coverify Systems Technology, where he provides verification services and works on creating viable opensource solutions for chip verification. Puneet is the main developer of Embedded UVM.

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