VSD - A complete guide to install Openlane and Sky130nm PDK
Requirements
- Need to complete this free course on Udemy for Linux virtual box installation and other dependencies "VSD - A complete guide to install open-source EDA tools"
- Windows or Linux OS. If its a Windows machine and Linux OS is not available, finish Udemy free course "VSD - A complete guide to install open-source EDA tools" for VLSI fundamentals
Description
This course is an extension of the free Udemy course, "VSD - A Complete Guide to Install Open-Source EDA Tools". While the initial course focuses on installing a variety of open-source tools, this course dives deeper into the specifics of installing the OpenLANE EDA toolchain and the open-process Sky130nm PDK. These tools, jointly released by Google and SkyWater Technology Foundry, are essential for anyone looking to get started with open-source silicon design.
The OpenLANE EDA toolchain is a powerful suite of tools designed to automate the digital design process from RTL to GDSII. It is based on several key components, including:
OpenROAD: A tool for physical design automation, enabling the creation of IC layouts from RTL.
Yosys: A popular open-source synthesis tool that converts high-level RTL code into gate-level netlists.
Magic: A layout tool that allows users to visualize and edit integrated circuit (IC) layouts.
Netgen: A netlist comparison tool that is used for layout vs. schematic (LVS) checks to ensure that the layout matches the design specifications.
Fault: A tool for fault analysis and testing.
Custom methodology scripts: Scripts that integrate and automate the flow between these tools, allowing for a smooth design process.
By the end of this course, you will have a complete understanding of how to install and configure OpenLANE and the Sky130nm PDK, empowering you to begin your own System-on-Chip (SoC) designs. The installation process is broken down into easy-to-follow steps, making it accessible even to those who are new to the field of EDA tools and IC design.
If you're working on a Windows machine, it’s important to first set up a Linux environment. To do this, you can refer back to the Udemy course, "VSD - A Complete Guide to Install Open-Source EDA Tools," which provides a step-by-step guide on how to install Linux on Windows using VirtualBox. This process will ensure you have the right environment to install and run the OpenLANE toolchain smoothly.
So, whether you're a beginner or an experienced designer, this course offers you the tools and knowledge to start designing your own chips—entirely free of cost.
Enjoy the videos, get your hands dirty with SoC design, and embark on your journey into the world of open-source IC design. All the best, and happy learning!
Who this course is for:
- Beginner in VLSI looking to work with open-source EDA tools and completed Udemy free course "VSD - A complete guide to install open-source EDA tools"
Instructors
Tips on order in which you need to learn VLSI and become a CHAMPION:
If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.
Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively
Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.
And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course
All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle
Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor
Connect with me for more guidance !!
Hope you enjoy the session best of luck for future
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.
Hands on with Technology @
1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.
2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.
3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer
4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.
5) “IR aware STA” and “Low power STA”
6) Analyzed STA engine behavior for design size up to 850 million instance count ACADEMIC
1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.
2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software
PUBLICATION
1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”
2) Concurrent + Distributed MMMC STA for 'N' views
3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit
4) Placement-aware ECO Methodology - No Slacking on Slack
ABOUT ME:
An Engineer by degree and a life-long student. A VLSI enthusiast focusing majorly on Physical Design domain. My work primarily revolves around block and SoC design planning using opensource EDA tools. Associated with three standalone PnR projects on Skywater 130nm and osu 180nm pdks and currently working on efabless' Openlane (RTL2GDS) flow project; aimed at complete automation of all stages from RTL to all the way down to GDSII.
AFFILIATIONS:
Research Intern at VLSI System Design (VSD) Corp. Pvt. Ltd.