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VLSI Physical Design: PnR with Cadence
Rating: 4.8 out of 5(8 ratings)
254 students

VLSI Physical Design: PnR with Cadence

From Netlist to GDSII: Learn Floorplanning, Placement, CTS, Routing, and Timing Closure using Industry-Standard EDA Tool
Created byElectronics Zone
Last updated 7/2026
English
English [Auto],

What you'll learn

  • Complete PnR Flow: Understand the step-by-step process of Physical Design from Netlist to GDSII.
  • Tool Proficiency: Gain hands-on experience with industry-standard Cadence PnR tools.
  • Floorplanning: Master techniques for die area estimation, I/O placement, and macro placement to optimize chip layout.
  • Power Planning: Design robust power grids (power stripes/rings) to mitigate IR drop and electromigration.
  • Placement Optimization: Perform standard cell placement and resolve placement-related congestion and timing issues.
  • Timing Analysis: Analyze static timing reports and apply optimization techniques to fix setup and hold violations.
  • Clock Tree Synthesis (CTS): Build balanced clock trees with low latency and skew.
  • Routing: Execute global and detailed routing to connect all nets without design rule check (DRC) violations.
  • Chip Finishing: Execute final steps including metal fill insertion and generating the final GDSII stream file for tape-out.

Course content

1 section • 10 lectures • 3h 58m total length

  • Place & Route Flow11:59

    Learn the place and route flow, transforming a post-DFT netlist into a physical gds file through six steps: floor planning, power planning, placement, CTS, routing, and finishing, with continual verification.

  • Input Files17:22

    Examine the input files that drive the PNR flow: the post-DFT netlist, timing libraries, constraints, and LEF data. See how these feed the tool for timing, placement, and routing.

  • Design Import23:51

    Import Verilog gate-level netlists, technology and standard cell left files, and constraints into the PNR tool, then configure MMMC analysis with library sets, RC corners, and analysis views.

  • I/O Placement & Specify Floorplan15:44

    Explore input-output pads with level shifters, buffers, and ESD protection, then define floor plans by core size, aspect ratio, utilization, and core to input-output spacing to optimize power and routing.

  • Power Planning12:59

    Explore power planning with rings, stripes, and rails to deliver VDD and VSS across the chip. Grasp the IR drop theory and Cadence PNR steps for rings, stripes, vias.

  • Placement17:35

    Master the placement stage in VLSI design with Cadence, learning to add placement blockages, place standard cells, and use tie cells to protect gates from supply noise.

  • Timing Analysis & Timing Optimization16:29

    Analyze and optimize timing across pre-cts, post-cts, and post-route stages to meet setup and hold targets, interpret wns and tns, and iteratively fix violations with echo-driven optimization.

  • Clock Tree Synthesis & Routing22:55

    Master clock tree synthesis to minimize skew with a buffer tree, meet design rule checks for maximum transition delay, load, and fan-out, and route with global and detailed steps.

  • Chip Finishing21:30

    Address antenna rule violations with metal jumping or diode insertion to protect gate oxide. Add filler cells and metal density fills, then generate post-PNR netlist, gds, and sdf for tapeout.

  • Final Practical PnR Lab using Cadence and exporting GDS1:17:40

    Perform the final practical PnR lab with Cadence and export the GDS file for fabrication.

Requirements

  • Basic VLSI Knowledge: Familiarity with the CMOS technology and the standard ASIC design flow (Frontend vs. Backend).
  • Digital Electronics: Understanding of basic logic gates, flip-flops, and combinational logic.
  • Linux Basics: Comfort with the Linux command line (navigating directories, editing files using vi/vim) as most EDA tools run on Linux.Linux Basics: Comfort with the Linux command line (navigating directories, editing files using vi/vim) as most EDA tools run on Linux.
  • Timing Concepts (Recommended): A basic understanding of Static Timing Analysis (STA) concepts like setup time, hold time, and clock skew is helpful but not mandatory, as these will be reviewed.

Description

USE PROMO "JUST-13"
Physical Design, commonly known as Place and Route (PnR), is a cornerstone of the VLSI (Very Large Scale Integration) industry. It is the stage where the logical representation of a circuit (the netlist) is transformed into a physical layout that is manufacturable. Mastering this flow is essential for anyone aiming to work as a Physical Design Engineer, CAD Engineer, or ASIC Flow Engineer.

This course offers a comprehensive, hands-on journey through the entire PnR flow, from initial data setup to final GDSII generation. We will utilize industry-standard Cadence tools to bridge the gap between theoretical VLSI concepts and real-world implementation. Unlike courses that focus solely on theory, this curriculum is structured to simulate the actual workflow of a physical design engineer. We will begin by understanding the critical input files—the netlist, LEF/DEF, and timing constraints (SDC)—that define the design.

From there, we will dive deep into the core stages of the flow. You will learn how to perform Design Import, followed by strategic Floorplanning where we define die area, core boundaries, and I/O placement. We will cover robust Power Planning to ensure reliable power distribution across the chip, preventing electromigration and IR drop issues. The course then moves into the algorithmic world of Placement, where we analyze congestion and timing. A significant portion is dedicated to Timing Analysis and Optimization, teaching you how to fix setup and hold violations before moving on to Clock Tree Synthesis (CTS) . Finally, we will navigate the complexities of Routing, handle Chip Finishing steps such as metal fill insertion, and conclude with a Practical Lab where you will run the full flow and export the final GDSII database. By the end of this course, you will have a portfolio-ready project and a deep understanding of how a chip is physically built.

Who this course is for:

  • Aspiring VLSI Engineers: Fresh graduates looking to secure a job in the Semiconductor industry as a Physical Design (PnR) Engineer.
  • Frontend Designers: RTL designers who want to understand the backend flow to become more well-rounded engineers or transition into physical design roles.
  • CAD Engineers: Engineers looking to understand the standard methodology to better support or develop automation scripts for PnR flows.
  • Freshers & Interns: Students currently in their final year of engineering who want to build a project in Physical Design to strengthen their resume.
  • Experienced Professionals: Engineers in adjacent fields (e.g., Verification, Test) who want to upskill and understand the chip implementation phase.

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