VLSI Design

Explain the complementary CMOS inverter, a simple not gate built from the pull-up network and the pull-down network, where zero yields one and one yields zero.

This lecture explains CMOS inverters, detailing the pull-down and pull-up networks and analyzing the voltage transfer characteristics (VTC) to show how input voltages map to output voltages.

Examine the inverter’s voltage transfer characteristic (VTC) and its five regions, from 0 to the threshold and beyond, to identify critical voltages and how input and output logic levels relate.

Explore the critical voltages of an inverter, including the maximum output, how zero input yields one, ranges for logic zero or one, and the transition and dead band with thresholds.

explores the pseudo NMOS inverter design, illustrating how input high grounds NMOS to pull the output down and input low allows the output to pull up.

Explore resistive-load inverters, where a pull-up resistor and a pull-down transistor realize inversion. The circuit remains static, pulling the output high for input zero and low for input one.

Examine static power in CMOS inverters in VLSI design, showing zero static current for inputs 0 or 1 because no path between Vdd and ground.

Analyze static power in a resistive-load inverter: high input causes current from Vdd to ground, while low input yields no static power.

Design complementary CMOS circuits using pull-up PMOS and pull-down NMOS networks. Apply network duality for parallel and series connections to implement NAND and AND operations.

Learn how to convert a multi-input boolean function into a CMOS circuit by designing complementary pull-down and pull-up networks, using series and parallel transistor arrangements for realizing logic.

Explore ratioed logic in vlsi design with pseudo nmos, where a grounded gate single transistor replaces the pullup network, yielding area reduction and a ratio-dependent output via transistor width ratios.

Explore the principle of pass transistors in VLSI design, where a control signal turns the path on to pass input to output, and off creates a high impedance state.

Learn to convert a boolean function into a VLSI circuit using pass transistors by turning expressions into sum of products, selecting control signals, and ensuring reliable output.

Discover how transmission gates address the weak one and threshold voltage drop issues in basic transistor logic, reducing output degradation and improving gate reliability.

Learn to realize any boolean function as a vlsi circuit using transmission gates, pairing nmos and pmos with complementary controls to implement and combine terms while avoiding threshold drop.

Explore dynamic circuits and their precharge and evaluation phases, where an externally clocked precharge transistor initializes the output and the evaluation transistor determines it.

Uncover the five characteristics of dynamic circuits. Learn how the pulldown network implements logic with input transistors, why there is no pull-up network, zero static power, and high switching speeds.

dynamic power in vlsi arises from switching, with zero static power in a seamless inverter; it scales with channel capacitance, switching frequency, and supply voltage, so lowering vdd helps.

Design a full adder using transmission gates, illustrating subsystem design and bottom-to-top VLSI methodology, deriving sum and carry expressions and implementing them with transmission gate logic.

Design a two-bit by two-bit array multiplier using complementary logic and vlsi techniques. Generate partial products, shift them, and add with half and full adders to obtain the four-bit product.

Explore how latches store a bit via the bistability principle; a D latch follows input when the clock is high and retains it when the clock is low.

Design a static d latch using transmission gates, capturing the d input on clock high and retaining the previous q on clock low via q and not q feedback.

Design a simple one-bit programmable shifter with left, right, and no-operation modes, using pass transistors, buffers, and latches.

Discover the basics of multiplexers as data selectors with multiple inputs and one output, driven by select lines. Understand truth tables, select lines, and 2x1 to 8x1 mux configurations.

Explore a simple transmission gate based implementation of a 2x1 mux using two transmission gates, passing inputs and their complements to the output according to the select signal.

Explore memory design concepts on a VLSI chip, including RAM/ROM classifications, DRAM, SRAM, and CAM, and how memory cells use word lines and bit lines to store and access data.

Explore a simple 4x4 rom cell design using word lines, bit lines, and transistors to read pre-written, non erasable data by selectively pulling up bit lines.

Explore random access memory concepts, including volatile storage and distinction between static RAM and dynamic RAM. Compare SRAM's six transistors per bit with DRAM's capacitor storage, cost and performance trade-offs.

Discover how a 6T SRAM cell stores a single bit using two cross-coupled CMOS inverters. Activate the word line to select the cell and drive the bit line to write or read, leveraging complementary CMOS logic to hold the data through cross coupling.

Explore how CMOS MOSFETs are transformed into VLSI layouts by using active regions, polysilicon gates, and metal contacts, following design rules, spacing, and color conventions.

Identify five basic color codes for layout design: green for active/diffusion regions, yellow for B+ regions, red for polysilicon gates, blue for metal and connections, and black for active contacts.

Convert a cmos inverter schematic to a Mead-Conway layout using two transistors, polysilicon, and metal layers. Apply lambda-based rules for widths, spacing, and active contacts, linking drains and grounding sources.

Design a current mirror with MOSFETs, using a diode-connected transistor to ensure saturation and copy a reference current; adjust the mirrored current via width and length ratios.

Explore dynamic power in vlsi design, coming from charging and discharging capacitances during switching, as dynamic power equals C Vdd^2 f, and contrast static power from short-circuit current during transitions.

Learn how clock gating reduces dynamic power in VLSI designs by using a decider circuit to enable or disable the clock to flip-flops, preventing unused blocks from switching.