VLSI - Design For Test (DFT)- JTAG, Boundary SCAN and IJTAG

Explains JTAG, the 1149.1 industry standard for verifying PCB designs after manufacture, featuring TAP controller, instruction register, and data registers such as boundary scan, device ID, and bypass.

Explore boundary scan, bypass, device ID, and user defined registers, and learn how test data registers use capture, shift, and update states to perform read and write operations.

Explore the 1149.1 tap, an on-chip FSM interface using signals TDI, TDO, TMS, Tkc and optional TR to read or write data and instruction registers via a 16-state scan.

Explore boundary scan design for 1149.1, enabling serial testing of chips, interconnects, and external circuitry without altering core logic, via a boundary scan chain linked to JTAG TDI/TDO.

Learn about ten boundary scan insertion instructions, four mandatory and six optional, and how instruction and data registers select boundary scan to test inter-chip interconnections via capture, shift, and update.

Introduce JTAG and IJTAG boundary-scan concepts, focusing on device interface, access network with tap controller and TDR bits, and instrument interface, plus key terms instrument, equal, and biddle.

Segment insertion bit (sib) converts the 1687 jtag network to a variable-length scan chain, enabling selective access to TDRs by gating with shift, update, and delay signals.

Explore the instrument connectivity language equal to model instrument access networks as modular hierarchies with ports and scan interfaces, including client and host interfaces and test data register behavior.

Explore procedural description language (piddle) for JTAG boundary scan, detailing level zero and level one commands, prefix handling, resets, reads and writes, and control structures.